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EDA Version 19.9.01 !!!!!!
This example is intended on TangMega 138KPro Modified DDR3 Board and Default Configuration Board
Aim: The example is continuously write and read back to check sanity of handshaking between DDR IP controller and custom FSM.
The debug methodology is address / 8 = write/read content app_data := {32{addr/8}}
How to capture? Setup the trigger address, and reset the FPGA board via the push button!
![image](https://private-user-images.githubusercontent.com/29487339/303438713-d983da1e-7761-4966-858a-4b51d9223dfb.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjIwNjU3NTYsIm5iZiI6MTcyMjA2NTQ1NiwicGF0aCI6Ii8yOTQ4NzMzOS8zMDM0Mzg3MTMtZDk4M2RhMWUtNzc2MS00OTY2LTg1OGEtNGI1MWQ5MjIzZGZiLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA3MjclMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwNzI3VDA3MzA1NlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTA2MmQxZmZkYjQ5NTlhODYzMjA0YjhjNmM0NWIwYWQ1Zjk5YjZiMjdiYjBlZTY1OTZiYmNlOGMxYjYzODg4MDUmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.qFh6wWo0HGMcUBxgp5T28JXB22mB7dGYA_AfJq2eSN4)
![image](https://private-user-images.githubusercontent.com/29487339/303407205-349fa9df-84fb-40d7-935f-b498e946cf5c.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjIwNjU3NTYsIm5iZiI6MTcyMjA2NTQ1NiwicGF0aCI6Ii8yOTQ4NzMzOS8zMDM0MDcyMDUtMzQ5ZmE5ZGYtODRmYi00MGQ3LTkzNWYtYjQ5OGU5NDZjZjVjLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA3MjclMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwNzI3VDA3MzA1NlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTQ3ZTQwNTRhZWZkMjdiZjFhN2ViNWQ2MjBjYjRjMzBkNGNhMWI3MzUyMmEwZTI1YWE2ZTIyNDAwMmMyNmI2MmImWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.h9l7-Qz5R2xZbHWJP7LC-ENZ0P9R4nJh57NgFBoMeHc)
Explain of MT41J128M16-125:K and IP configuration
![image](https://private-user-images.githubusercontent.com/29487339/303438451-2da3f0b3-620e-48a2-b95d-d83e7d76b6fd.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjIwNjU3NTYsIm5iZiI6MTcyMjA2NTQ1NiwicGF0aCI6Ii8yOTQ4NzMzOS8zMDM0Mzg0NTEtMmRhM2YwYjMtNjIwZS00OGEyLWI5NWQtZDgzZTdkNzZiNmZkLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA3MjclMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwNzI3VDA3MzA1NlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTBjMWQ0YWRhZDljMTliYjAzYTk0ZDEzNTc1YjY0ZTY4ZjhmNTk4OWQ0NmJhOTViNjQ1YWZmYWQ2M2MxOTE4ODkmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.PwqbN2_HCggh1r9WSa8hP8WIcXxh8Fwmzu6h7NfyDxA)
Explain of H5TQ4G63EFR-RDC and IP configuration
Because the suffix of the DDR3 is RD and C with support of previous DDR speed.
For tCKE the datasheet does not clearly mention any data, from general rule of DDR3 mostly about 3N of tCK.