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View Code? Open in Web Editor NEWAn FPGA accelerator for all-pairs shortest-paths (using the Floyd-Warshall algorithm) - a systolic array based parallel design
License: Apache License 2.0
An FPGA accelerator for all-pairs shortest-paths (using the Floyd-Warshall algorithm) - a systolic array based parallel design
License: Apache License 2.0
Hello,
first I wanted to thank you for posting the verilog code of the floyd-warshalI algorithm. I remarked that in the pe_instr_decoder and in the pe files the statements of the commands cases have the same bits B'000 for READ0, READ1 and Compute I couldn't understand the purpose of doing so since when using a case statement one has to put different statements (different bits) and the behaviour will change according to the statement chosen. Is it a mistake ? if not could you please explain to me how does it work ? what is the purpose of doing so ?
Thank you very much.
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