bolifeyo / 5-stage_risc-v_processor Goto Github PK
View Code? Open in Web Editor NEWThis project forked from robbruern/5-stage_risc-v_processor
Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor.