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CENG3420 Project Phase 1 Readme file

Group number: 	24
Group member: 	ZHOU Wei 1155014575
		WANG Yuxi 1155014399

memtable.vhd, processor.vhd, processor_tb.vhd, regtable.vhd:
		VHDL files provided as skeleton code.

ALU.vhd:
		Simulating an ALU component.

mux.vhd:
		Simulating an multiplexor.

aluControl.vhd:
		Simulating the ALU control component.

control.vhd: 
		Simulating the control component.

processor_core.vhd:
		Including all relevant port map and core processes.