John Samuel Ebenezer's Projects
Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
ABC: System for Sequential Logic Synthesis and Formal Verification
Verilog ADC interface for adc128s022 found in De0 Nano
Verilog for using an ADC to sample analog video and output to a digital display (VGA, HDMI, etc.)
Config files for my GitHub profile.
RISC-V manycore accelerator for HERO, bigPULP hardware platform
This is the repo for submitting your CAD Algorithms
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
A Graphical User Interface for data visualization for clock tree synthesis
Builds a congestion map for guide files which gives the routes of various nets in the chip design. Clock tree topology for nets from DEF file.
SweRV EL2 Core
FuseSoC-based SoC for SweRV EH1
CPU design with SystemVerilog/UVM verification
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
The Leek group guide to data sharing
Standard Cell Library based Memory Compiler using DFF cells
A collection of phase locked loop (PLL) related projects
The Ultra-Low Power RISC-V Core
This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
An abstraction library for interfacing EDA tools
Educational materials for RISC-V
FOSS Flow For FPGA
Fiduccia Mattheyses Algorithm Implemntation in C++
EDA - a simulated annealing algorithm of floorplaning in IC design