It looks like its redirecting to zedboard.org but that seems to be down. I did find App Note 1 - which might be the right one?, however step 11 has this "that we will be using in the next application note"; I can't find the follow on app note - is there a link somewhere?

According to the MiniZed_Petalinux_HDF_2017_1_02-Tutorial.pdf, I need to clone this HDL repository from the minized_petalinux_MINIZED_20170810_010906 tag.

This tag is not longer present, which one has replaced it?

Hi,
I am trying to make the design pzfmc2 hdmi design on vivado 2017.4 with the help of "make_pzfmc2_hdmi.tcl", after running this tcl file it gives me error

ERROR: [Board 49-71] The board_part definition was not found for em.avnet.com:picozed_7030:part0:1.0. The project's board_part property was not set, but the project's part property was set to xc7z030sbg485-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

while executing

"source ./ProjectScripts/$project.tcl -notrace"
("PZ7030_FMC2" arm line 2)
invoked from within
"switch -nocase $board {
PZ7015_FMCCC -
PZ7030_FMCCC -
PZ7010_FMC2 -
PZ7020_FMC2 ..."
(file "./make.tcl" line 306)

while executing

"source ./make.tcl -notrace"
(file "./make_pzfmc2_hdmi.tcl" line 51)

I have down loaded the latest 2017.4 bdf from "https://github.com/Avnet/bdf" and added them to the folder "Xilinx/Vivado/2017.4/data/boards/board_files"

Not able to figure out the issue, Please help me to resolve this issue.

Hi,

I am currently trying to port the design to Vivado 2015.4, but it does not support the tpg 6.0 core. The new TPG core only has one clock input. What should I do?

Hi,

For the project embv_p1300c in the Avnet/hdl repository: It seems that there are 2 FIFOs that appear in the netlist as black boxes. These are within the onsemi_vita_cam module; afifo_64i_16o and pulse_regen. Both these module have VHDL files that call out the fifo_generator_v13_0_1 library. I assume these are simulation models for the FIFOs, but they result in black boxes in the netlist. Are there XCI files missing from the repository?

Thanks,
Rich Keefe

In the newest version of this repository, the IP core is generated with the newer version of the VIVADO. However, some of the project for example FMCCH are only compatible with VIVADO 2015.4, which is not able to read the new IP core. I have to get back to the old version of the ipcore to get your reference design work. Please fix it, it is confusing.

We have used Avnet HDMI output (PicoZed Smart Vision Development Kit) on display screen is fluctuating what could be probable reasons behind this problem, based on FMCHC_python_1300 project with external camera interface.
Check demo video of V_20171205_105538.mp4: http://community.avnet.com/t5/FMC-HDMI-I-O-VITA-Image-Sensor/Fluctuating-display/td-p/18676

Hello!

When running the make_fmc_imageon_gs.tcl in the Vivado 2018.1 tcl client for ZEDBOARD (after updating the ip block minor versions difference between Vivado 2015.4 and Vivado 2018.1 in the fmc_imageon_gs_bd.tcl script) I get the following errors:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 192 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: IO_HDMII_clk_1.

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 192 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: IO_HDMII_clk_1.

The port in question is not an accually port but is created after the synt and impl step. The port IO_HDMII_clk exists however and does have valid constraints and I/O standard. The addition of the '_1' in the name (which happens somewhere and I dont know why and where) yields IO_HDMII_clk_1 which in the constraint file is not declared with any set_property specific options (since it is unknown at the constraint creation time) and thus breaks the bitstream generation.

Do you know why and where in the tcl scripts the '_1' is introduced to the name and are there any other reasons for this addition?

/AvH

The most recent (Vivado v15.4) uZed Embedded Vision (embv) Kit HDMI tutorial mentions a GitHub repository with the tag, "embv_hdmi_passthrough_MZ7020_EMBV_20160223_195702". This tag does not appear in the Avnet/hdl repository. Similarly, Python-1300-C Frame Buffer design tutorial uses the tag, "embv_p1300c_MZ7020_EMBV_20160223_205955", but is also has no file set. In fact, the simple tag seach for "embv" comes up empty. Does anybody know what has become of the EMBV file sets?

Thanks for providing these well done scripts. I assume these have been tested on Windows (filesystem is case insensitive). That said, when running source make_minized_foundation.tcl on Linux, I got

...
couldn't read file "../Boards/minized/minized.tcl": no such file or directory
...

The actual folder is ../Boards/MINIZED/MINIZED.tcl. Renaming the path to ../Boards/minized/minized.tcl fixed it.

We interfaced slb 9670 with Msp430 16 bit controller through spi which does not support Linux Kernel.

Our Main Task , is store a few bytes of data securely into SLB 9670

Now we able to access the spi communication of slb 9670 with controller,

we tested the reading sample registers of slb 9670 like DIDVID register , version id of slb 9670, status register and writing a values into registers through spi communication.

so spi read and spi write communication is working with chip by accessing this registers.

Our Main Task , is store a few bytes of data into SLB 9670 , so by referring by documents of TCG stack i am not able to understand what steps should i follow to complete our task .

As per documents i am able to understand that we should store data in NV Memory , types of keys and hash algorithms in tpm chip.

so kindly help me at what are required steps , should i follow ?

can you share any documents rather than datasheets or any libraries from your side to simplify our task?

thanks for your support