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asmdb's Issues

remove instruction ltr r32/m16, ltr r64/m16

Hi kobalicek:
there are 3 ltr items in asmdb:

ltr"              , "R:r16/m16"                                   , "M"       , "66 0F 00 /3"                      , "ANY              Volatile PRIVILEGE=L0
ltr"              , "R:r32/m16"                                   , "M"       , "0F 00 /3"                         , "ANY              Volatile PRIVILEGE=L0
ltr"              , "R:r64/m16"                                   , "M"       , "REX.W 0F 00 /3"                   , "X64              Volatile PRIVILEGE=L0

intel manual speaks:

The operand-size attribute has no effect on this instruction.
In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the 64-bit base.

AMD manual says:
The operand size attribute has no effect on this instruction

I checked out it within nasm and fasm. Both report error.
nasm: illegal instruction
fasm: invalid size of operand.

Instructions missed implicit operands info

popa, popad pop 8 generals
pusha, pushad push 8 generals

Maybe need a new registers flag string?
seems "all" not an option, because call instruction and others maybe redefine the semantics of "all"
xx/yx/zx like series for cases?

And
vzeroall
vzeroupper
need a "all" kind of symbol to flag it.

possible typo in movq (and maybe movd is as well)

movq is the only instruction using this descriptor: r64[63:0]/m64
"movq" , "W:xmm[63:0], r64[63:0]/m64"

should this be just r64/m64 ? Especially since the MR variant looks like:
"movq" , "W:r64/m64, xmm[63:0]"

movd seems also suspicious:
"movd" , "W:r32[31:0]/m32, xmm[31:0]"
"movd" , "W:xmm[31:0], R:r32[31:0]/m32"

but the use of r32[31:0] sees to be more widespread,

Support for jmp, call, and ret [far] instructions

hello,
as this project effect's asmjit, i've created the issue here, not in asmjit, (because asmjit get's it's instruction sets from here)
some of the instructions like hlt, iret, and some others are not implemented in the asmjit
if these are implemented, asmjit can be like nasm, which is used to write operating systems
look at this and it should be easy to add these

suggestions for making the format field ("M", "RM", "MR", etc) more useful

For my project (based on asmdb) it has been very useful to locally rewrite the format field to satisfy the following invariant:

  • the number of characters in the format field equals the number of operands.
    This is violated for implicit operands, e.g.:
 "div"              , "X:<edx>, X:<eax>, r32/m32"                       , "M"       , "F7 /6"

My suggestion would be to change the format field to something like: "xxM" where "x" represents an implicit operand.

There also seems to be a problem with these opcodes:

    ["mov"              , "w:r8, ib/ub"                                     , "I"       , "B0+r ib"                      , "ANY"],
    ["mov"              , "w:r16, iw/uw"                                    , "I"       , "66 B8+r iw"                   , "ANY"],
    ["mov"              , "W:r32, id/ud"                                    , "I"       , "B8+r id"                      , "ANY"],
    ["mov"              , "W:r64, iq/uq"                                    , "I"       , "REX.W B8+r iq"                , "X64"],

I believe the format should be ""OI"

confusion around x86 "and" instructions

These two seem to conflict:

["and" , "X:r32/m32, id/ud" , "MI" , "81 /4 id" , "ANY _XLock OF=0 SF=W ZF=W AF=U PF=W CF=0"],
["and" , "X:r64, ud" , "MI" , "81 /4 id" , "X64 _XLock OF=0 SF=W ZF=W AF=U PF=W CF=0"],

What does 0 and U mean on the flags?

Wondering what 0 and U mean on the metadata for the flags, as in:

OF=U SF=U ZF=U AF=U PF=U CF=U
OF=0 SF=W ZF=W AF=U PF=W CF=0

Also what do the lowercase x vs. uppercase X mean, and lowercase w and W?

x:~r8/m8,~r8

Enough metadata for codegen?

Hi there!
Looking at the database x86data.js and I was wondering if the file has enough information to generate a proper x86/x64 code generator? (assuming that the /0, ib, /r...etc. have to be "handcoded")... as it looks like you are using it for asmjit (for the generate-XXX.js), I believe that it should be ok, but just want to be sure!
Thanks!

call vs jmp format inconsistency

For (indirect) jmps the format is "D":

 ["jmp"              , "R:r32/m32"                                       , "D"       , "FF /4"                        , "X86 BND          Control=Jump"],
 ["jmp"              , "R:r64/m64"                                       , "D"       , "FF /4"                        , "X64 BND          Control=Jump"],

But calls the format is "M":

["call"             , "R:r16/m16"                                       , "M"       , "66 FF /2"                     , "X86 BND          Control=Call OF=U SF=U ZF=U AF=U PF=U CF=U"],
 ["call"             , "R:r32/m32"                                       , "M"       , "FF /2"                        , "X86 BND          Control=Call OF=U SF=U ZF=U AF=U PF=U CF=U"],
 ["call"             , "R:r64/m64"                                       , "M"       , "FF /2"                        , "X64 BND          Control=Call OF=U SF=U ZF=U AF=U PF=U CF=

I think it should also be "M" for indirect jmps

xlat and xlatb

I would suggest just having xlat [es:zbx + al] signature and remove xlatb completely (it's alias anyway).

armdata.js marks "blx label" as available in ARMv4

armdata.js marks "blx label" as available in ARMv4:

["blx" , "#RelS*4" , "T32", "1111|0|RelS[22]|RelS[19:10]|11|Ja|0|Jb|RelS[9:0]|0" , "ARMv4T+ IT=OUT|LAST"],
["blx" , "#RelS*2" , "A32", "1111|101|RelS[0]|RelS[24:1]" , "ARMv4+"],

but I used to work with ARM7TDMI and I think that did not have BLX, and here ARM states that "This instruction is available in all T variants of ARM architecture v5 and above."

Shouldn't it then be "ARMv5T+" in both cases? "bx register" seems to be correct.

suggestion for movss and movsd and possibly other similar case

Current movss is reflected in the table as:

    ["movss"            , "w:xmm[31:0], xmm[31:0]"                          , "RM"      , "F3 0F 10 /r"                  , "SSE"],
    ["movss"            , "W:xmm[31:0], m32"                                , "RM"      , "F3 0F 10 /r"                  , "SSE"],

Wouldn't it be more systematic to fold them into one entry:

    ["movss"            , "w:xmm[31:0], xmm[31:0]/m32"                          , "RM"      , "F3 0F 10 /r"                  , "SSE"],

There is also a strange asymmetry where the MR variant only has the W:m32 flavor. Not sure if this is an
ISA quirk or a transcription error:

["movss"            , "W:m32, xmm[31:0]"                                , "MR"      , "F3 0F 11 /r"                  , "SSE"],

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