This is a single-precision (Sp) and a double-precision (Dp) floating point unit (FPU) which could perform the main floating-point operations. The whole FPU is implemented in Verilog HDL.

This project is a group project as a part of the Logic Design II (CMPN111) course at Cairo University. The project requirement description is available here.

• Features
• Design
• Implementation
• How to run the project

• Single-precision (Sp) and double-precision (Dp) floating point unit (FPU)
• Detecting and handling of special cases
• Addition
• Subtraction
• Multiplication
• Division

The design of the FPU is described in the Design document.

The guidelines for implementing the FPU are described in the Implementation document.

The project is implemented in Verilog HDL and is tested using the ModelSim simulator. To run the project, you need to have ModelSim installed on your computer. Then, you need to open the project in ModelSim and add the .v files to the project. After that, you need to compile the project and run the testbenches.

• Ahmed Emad
• Hla Hany
• Hossam Nabil
• Khaled Mamdouh