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A eurorack-friendly audio frontend compatible with many FPGA boards.

Home Page: https://apfelaudio.com/modules/available/pmod/

License: Other

Makefile 4.96% Python 26.27% SystemVerilog 49.92% Shell 1.43% OpenSCAD 12.97% Verilog 4.45%

electronics eurorack fpga hardware modular-synthesizers cocotb kicad synthesizer verilog yosys pmod

eurorack-pmod's Introduction

Eurorack PMOD

Eurorack PMOD is a certified open hardware Eurorack module that plugs directly into many FPGA boards, which makes it easy to combine the world of FPGAs and hardware electronic music synthesis. The latest (R3.3) hardware looks like this and can be ordered here.

How does it work?

Plug eurorack-pmod into an FPGA development board of your choice. Here is a list of boards already supported by the examples.
Get started with some example DSP cores. Examples include calibration, sampling, effects, synthesis sources and so on. The design files can be synthesized to a bitstream using Yosys' oss-cad-suite.

🎶 Project Showcase ✨

FPGA-based neural-net waveshaper - (from matpalm@)
Daisy Seed TDM for Eurorack PMOD - (from heartwerker@)
apu_chord core - (from proppy@)

A couple more from me:

8-channel USB2 soundcard - mostly in Amaranth.
Real-time DSP with Rust on LiteX - mostly in Rust/Migen.

R3.3 hardware details

3HP module compatible with modular synthesizer systems.
- Module depth is 35mm with both ribbon cables attached.
PMOD connector compatible with many FPGA development boards.
8 (4 in + 4 out) DC-coupled audio channels, 192KHz / 32bit sampling supported.
PWM-controlled, user-programmable red/green LEDs on each output channel.
Jack insertion detection on input & output jacks.
Calibration EEPROM for unique ID and storing calibration data.
[new!] Touch and proximity sensing on all unused jacks as an extra input method.
- See the gateware/cores/touch_cv.sv core for an example of how to use this.

Compared to R3.1, the changes across R3.2 and R3.3 are summarized here

Want one?. More photos can be found below.

Included examples

This repository contains a bunch of example DSP cores which are continuously being updated:

gateware/cores/pitch_shift.sv - Pitch shifter
gateware/cores/filter.sv - Filter (low pass + resonance)
gateware/cores/touch_cv.sv - Touch sensing to CV converter
gateware/cores/clkdiv.sv - Clock divider
gateware/cores/sampler.sv - .wav sampler
gateware/cores/seqswitch.sv - Sequential routing switch
gateware/cores/digital_echo.sv - Echo / delay effect
gateware/cores/vca.sv - VCA (voltage controlled amplifier)
gateware/cores/vco.sv - VCO (voltage controlled oscillator)
gateware/cores/bitcrush.sv - Bitcrusher

These examples can all run out of the box on the development boards listed below.

Choosing an FPGA development board

An FPGA development board itself is NOT included! Essentially anything iCE40 or ECP5 based that has a PMOD connector will support the open-source tools and the examples in this project. Just make sure you have enough LUTS, >3K is enough to do interesting things.

The following development boards have been tested with eurorack-pmod and are supported by the examples in the github repository

iCEbreaker (iCE40 based)
ECPIX-5 (ECP5 based)
Colorlight i5 (ECP5 based)
Colorlight i9 (ECP5 based)
pico-ice from TinyVision (iCE40 based)
CCGM1A1 Gatemate EVB from CologneChip - experimental! see here

PMOD Pinout

The PMOD pinout is on the silkscreen on the back side of the board. Details are below. Note that Pin 1 is the SQUARE pad.

SDI (AK4619VN SDIN1)
SCL (I2C SCL for AK4619VN CODEC, EEPROM, LED + JACK IO expanders)
SDO (AK4619VN SDOUT1)
SDA (I2C SDA)
LRCK (CODEC clock line)
PDN (CODEC power down, also connected to LED output enable and JACK reset line -- HIGH means everything is on)
BICK (CODEC clock line)
MCLK (CODEC clock line)
GND
GND
3V3 IN
3V3 IN

Getting Started

I have tested builds on Linux, Mac and Windows (under MSYS2). All are tested in CI.

Install the OSS FPGA CAD flow.
- You may be able to get yosys / verilator from other package managers but I recommend using the releases from YosysHQ so you're using the same binaries that CI is using.
- On Linux, once the YosysHQ suite is installed and in PATH, you should be able to just use make in the gateware directory.
- On Windows, CI is using MSYS2 with MINGW64 shell. Install MSYS2, MINGW64, extract the oss-cad-suite from YosysHQ and add it to PATH. Then you should be able to use make in the gateware directory.
- Note: The gateware is automatically built and tested in CI, so for either platform it may be helpful to look at .github/workflows/main.yml.
Build or obtain eurorack-pmod hardware and connect it to your FPGA development board using a ribbon cable or similar. (Double check that the pin mappings are correct, some ribbon cables will swap them on you! Default pinmaps are for the ribbon cables I shipped with hardware, you need to flip the pinmaps for a direct connection PMOD -> FPGA)
Try some of the examples. From the gateware directory, type make to see valid commands. By default if you do not select a CORE it will compile a bitstream with the 'mirror' core, which just sends inputs to outputs. Note, you'll need to run git submodule update --init --recursive from the repo root after checkout.
Calibrate your hardware using the process described in gateware/cal/cal.py. Use this to create your own gateware/cal/cal_mem.hex to compensate for any DC biases in the ADCs/DACs. (this step is only necessary if you need sub-50mV accuracy on your inputs/outputs, which is the case if you are tuning oscillators, not so much if you are creating rhythm pulses.

Project structure

The project is split into 2 directories, hardware for the PCB/panel and gateware for the FPGA source. Some interesting directories:

gateware/cores: example user core implementations (i.e sequential switch, bitcrusher, filter, vco, vca, sampler etc).
gateware/top.sv: top-level gateware with defines for selecting features.
gateware/cal/cal.py: tool used to calibrate the hardware after assembly, generating calibration memory.
gateware/drivers: driver for CODEC and I2C devices used on this board.
hardware/eurorack-pmod-r3: KiCAD design files for PCB and front panel.
hardware/fab: gerber files and BOM for manufacturing the hardware.

Manufacturing

R3.3 hardware is in stock order here :)

R3.1 Hardware (no longer manufactured)

The above README focuses on R3.3, which is currently being manufactured.

Revision R3.1 was sold out in 2023. It's no longer manufactured, however this repository still supports it if you use the HW_REV=HW_R31 flag when building. I left some of the old photos here in case they are useful.

From the gateware perspective, there is almost no difference between R3.1 and R3.3 and so any cores should be compatible with both (unless they use new features of R3.3 e.g. touch sensitive jacks).

R3.1 boards

R3.1 hardware details

R3.1 technical

3HP module compatible with modular synthesizer systems.
- Module depth is 47mm with both ribbon cables attached
- This fits nicely in e.g. a 4MS POD 48X (pictured below).
PMOD connector compatible with most FPGA development boards.
8 (4 in + 4 out) DC-coupled audio channels, 192KHz / 32bit sampling supported.
PWM-controlled, user-programmable red/green LEDs on each output channel.
Jack insertion detection on input & output jacks.
Calibration EEPROM for unique ID and storing calibration data.
I/O is about +/- 8V capable, wider is possible with a resistor change.

Known limitations

Moved to github issues

Photos

`eurorack-pmod` R3.1 connected to iCEBreaker

License

Hardware and gateware are released under the CERN Open-Hardware License V2 CERN-OHL-S, mirrored in the LICENSE text in this repository.

If you wish to license parts of this design in a commercial product without a reciprocal open-source license, or you have a ground-breaking idea for a module we could work on together, feel free to contact me directly. See sebholzapfel.com.

The above LICENSE and copyright notice does NOT apply to imported artifacts in this repository (i.e datasheets, third-party footprints).

eurorack-pmod's People

Contributors

Stargazers

Watchers

Forkers

metamorphart proppy matpalm sangibeaud saicharan0112 jojo535275 juanmaneo hrupprecht

eurorack-pmod's Issues

Hardware R3.2/R3.3 bringup: changelist + notes

proto1 looks like this:

I will submit a production batch for R3.3 likely in the next month or 2.

Design / Gateware bringup

Working gateware: this repo, branch seb/r32-bringup
R3.2 hardware design: this repo, branch seb/capsense-groundfix
Gateware for proximity/touch-sensitive jacks! (experimental) this repo, branch seb/touch-fsm

R3.2 Hardware Changelist

feature: smaller / skiff friendly form factor: total module depth (to the end of the pin headers) is drastically reduced from 45mm to about 32mm. This fits in a lot more skiff/thin eurorack cases.
feature: proximity + touch sensitive jacks (demo): any unused jacks can be used as proximity/touch sensors as an extra input method (I think this has never been done in Eurorack - but I always wanted to see if it's possible..). They are continuously sensitive from ~5mm away from the jack and emit continuous values 0-255. This increases audio noise a little bit, but the feature is switched off by default in the first branch above. Individual channels can also be dynamically switched on-off.
feature: auxiliary flat-flex connector on bottom-side: all power nets and PMOD pins are broken out on an auxiliary connector underneath the board, this is intended for future daughterboards containing an FPGA/host to bolt onto the PMOD and extract power from the PMOD power connector.
feature: internal post-scaler loopback: whenever both in/out jacks on a particular channel are not connected, inputs are automatically connected to outputs. This simplifies self-calibration, but I don't like how it affects noise performance, so I might remove this for the next revision.
bugfix: scaler network adjustments. Previously eurorack-pmods were about 1V out from zero without calibration. Now all PMODs should be statistically close to zero even without calibration (but still require it for mV-level accuracy). This also buys us more in/out swing range, and because I also reduced the scaler amplitudes, improves noise performance.
bugfix: fix routing error on star ground: this required manual rework on R3.1 and is no longer a problem. This also improves audio noise performance.

Known bugs R3.2

Touch sensor pad routing for input channel 0 is too close to the shifter network, so has higher noise coupling than the other channels, this will be fixed for R3.3. Doesn't limit functionality unless you listen at super high volume
I2C touch sensor likes to send seemingly random NACKs, which is expected from the datasheet, but without the custom gateware above this causes flickering of the LEDs unless you A) turn off the touch sensing IC or B) condition the I2C state machine on requiring ACKs for every step.

hardware/r3.3: jack 2 during cold powerup causes touch IC to stay in reset

I noticed recently during some testing that if I power cycle the whole modular system with an FPGA design saved in flash, if jack input 2 (starting at 0) is inserted before power up, eurorack-pmod does not start correctly because the touch IC rejects all I2C requests. Removing jack 2 instantly allows it to boot.

Interestingly, a software reset with jack 2 inserted after successful boot seems to work fine, so it's only a power on reset that seems to be affected by this. The root cause of this is probably that the CS2 is shared with AXRES unlike all the other touch pads, which per the datasheet means that the shield of jack 2 should NOT be permitted to be grounded during boot.

2 actions:

for the next revision (R3.4), revise jack 2 so the touch pad is never grounded during bootup
for the current revision, modify gateware to not perform touch IC initialisation until jack 2 is removed and add a note to the readme about this behaviour.

This way, everything still works fine even if jack 2 is inserted after a cold boot, just the touch sensing will not work until jack 2 is replugged.

power fpga board from the 5v eurorack connector

I noticed that the 5v power line on the eurorack connector is grounded, is that intentional?

I'd love to be able to power the dev board directly from the eurorack supply? (or is a #badidea?)
Also curious if something like the https://github.com/tinyvision-ai-inc/pico-ice would be cool with receiving 3.3V directly from the pmod connector.

UART mirroring on pico-ice-v3

The pico-ice-v3 board has an RP2040 between the iCE40 and USB port with emulated serial.

The calibration tool needs to be tested using the UART mirror through the RP2040, might need to change the baud rate to ensure it gets mirrored correctly.

This firmware for the RP2040 should do it https://github.com/tinyvision-ai-inc/pico-ice-sdk/tree/6ef9518a3d6a64894ddc7af0d36fad5698755ada/examples/pico_usb_uart

problem is it runs at 115200, whereas all examples use 1MBit UART baud rate

Faust support?

Maybe a bit of an odd question. Since Faust can be compiled to run on FPGA hardware, would it be possible to target your board as well?

https://fast.grame.fr/results/processor.html

Add pmod pinout to readme

Hello,

I'm having trouble finding the pinout for the pmod connector. That is, which of the pins is used for which signals. If it's documented I haven't found it yet. I'm sure I could determine it by opening the schematic or reverse engineering one of the board files. But I feel that this is basic information that anyone using a different board will want to know, so it should be clearly documented somewhere obvious like the readme.

To go above and beyond, it would be great to have an annotated photo or diagram to make it totally clear which pin is which. But that's not necessary, a clear text description would be sufficient.

add support for ICE-V-Wireless

what would be needed to add support for https://github.com/ICE-V-Wireless/ICE-V-Wireless ?

would changing the pinmap be enough?

looking at https://github.com/ICE-V-Wireless/ICE-V-Wireless/blob/main/Gateware/blinky_demo/icestorm/Makefile#L11-L12 it seems based on the same part than the icebreaker.

ps: thanks for the pictures of berlin!

make calls icepack but not iceprog?

git clone [email protected]:apfelaudio/eurorack-pmod.git
# commit ec676d6eed92159870c07cd1b16ddc0b48d029ef
cd eurorack-pmod
git submodule update --init --recursive
cd gateware
make BOARD=icebreaker CORE=mirror

runs yosys, nextpnr and icepack, but not the final iceprog?

mkdir -p build/icebreaker
# For now we always force a re-build since we can pass different DSP cores
# through environment vars and we need a re-build to happen in this case.
make -B -f boards/icebreaker/Makefile BUILD=build/icebreaker CORE=mirror 
make[1]: Entering directory '/home/mat/dev/eurorack-pmod/gateware'
yosys -f "verilog -sv "-DSELECTED_DSP_CORE=mirror -DINVERT_BUTTON=1 -DICE40"" -ql build/icebreaker/top.log -p 'synth_ice40 -dsp -top top -json build/icebreaker/top.json' top.sv boards/icebreaker/sysmgr.v eurorack_pmod.sv drivers/pmod_i2c_master.sv drivers/ak4619.sv external/no2misc/rtl/uart_tx.v external/no2misc/rtl/i2c_master.v cal/cal.sv cal/debug_uart.sv cores/mirror.sv cores/clkdiv.sv cores/seqswitch.sv cores/sampler.sv cores/bitcrush.sv cores/vca.sv cores/vco.sv cores/pitch_shift.sv cores/stereo_echo.sv cores/filter.sv cores/util/filter/karlsen_lpf_pipelined.sv cores/util/filter/karlsen_lpf.sv cores/util/transpose.sv cores/util/echo.sv cores/util/delayline.sv cores/util/dc_block.sv cores/util/wavetable_osc.sv
Warning: Yosys has only limited support for tri-state logic at the moment. (top.sv:126)
Warning: Yosys has only limited support for tri-state logic at the moment. (top.sv:127)
Warning: Resizing cell port $paramod\debug_uart\DIV=s32'00000000000000000000000000001100.utx.div from 32 bits to 8 bits.
Warning: Resizing cell port top.eurorack_pmod1.force_dac_output from 32 bits to 16 bits.
nextpnr-ice40 --up5k \
--package sg48 \
--json build/icebreaker/top.json \
--pcf boards/icebreaker/pinmap.pcf \
--asc build/icebreaker/top.asc \

_<snipped lots of nextpnr output >_

Info: Max delay <async>                     -> posedge PMOD_MCLK$SB_IO_OUT: 14.85 ns
Info: Max delay posedge $PACKER_GND_NET     -> posedge PMOD_MCLK$SB_IO_OUT: 16.14 ns
Info: Max delay posedge PMOD_MCLK$SB_IO_OUT -> <async>                    : 10.75 ns
Info: Max delay posedge PMOD_MCLK$SB_IO_OUT -> posedge $PACKER_GND_NET    : 16.14 ns

Info: Program finished normally.
icepack build/icebreaker/top.asc build/icebreaker/top.bin
make[1]: Leaving directory '/home/mat/dev/eurorack-pmod/gateware'

but can run iceprog explicitly ok?

$ iceprog build/icebreaker/top.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0xEF 0x40 0x18 0x00
file size: 104090
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
programming..
done.                 
reading..
VERIFY OK             
cdone: high
Bye.

it's in the Makefile, but isn't run?

Support builds on Windows + Mac

Currently only builds on Linux are tested, however it should be relatively trivial to support other operating systems.

I just tried installing oss-cad-suite and MSYS2 on a Windows VM and was able to build the examples in this repository fine, with the following notes:

Must change all relative paths of .hex files such that they are relative to top-level makefile
Do all building under MSYS2 MINGW64 shell, adding oss-cad-suite bin/lib directories to PATH
After doing this, 'make' seems to work fine

Ideally we should add Windows/Mac targets to CI as well so they stay healthy

ak4619/cal: test sample widths other than W=16

Initially raised in #37

There's nothing limiting us to W=16-bit samples (maximum from AK4619 is 32 bits per sample).

We should try some different sample widths and make sure the rest of the modules (calibrator, demos) all still work.

The calibrator module cal.sv would need to be modified to be parameterized across different fixed-point representations.

R3.1 hardware limitations and R3.2 changes

Some things to change/update for R3.2 hardware:

R3.2 hardware changes

Fix routing error which requires 0 ohm resistor between GND/GNDD
- Context: R3.1 boards are modified such that L4 is a 0 ohm resistor, otherwise there is too much ground bounce due to the LED PWM switching. This is caused by the decoupling caps around the PWM controller being (incorrectly) on GND instead of GNDD. Interestingly the board works even without this change and the noise isn't worse, but the CODEC sometimes will randomly shut down due to the ground bounce if L4 isn't swapped (it is already correctly reworked by hand on all units I have shipped).
Move VCOM reference voltage closer to the statistical center of the AK4619 ADC inputs. At the moment the VCOM voltage is a few hundred mV away from the statistical zero of the DC center of the ADC inputs.
- This has no effect after calibration, but it means that with no zero calibration, the raw counts are about 1V away from where they should be, and means we get less input swing in one direction on the inputs.
General noise improvements. At the moment there is room for improvement on R3.1 noise performance. Noise is clearly audible if I turn up the gain on my Befaco OUT module into headphones all the way up to max. Qualitatively the noise sounds about the same as my MI Beads, but clearly worse than my ES Disting. Some ideas:
- Removing the GNDD/GND tie should reduce noise
- Switching to 48KHz sampling (this actually does audibly reduce noise a fair bit, I tried it)
- Reduce input/output swing. At the moment +/- 10V capability is really hurting our noise performance. Maybe most people don't care and we can do +/- 7V or so which would quieten things down considerably
- Investigate input/output op amp source/load impedances

R3.2 new features (maybe)

add 3V3 regulator that can optionally power a connected FPGA board
add some diodes such that the op-amps are powered from 3V3 if no +/-12V rails connected (so the analog sections still work if nothing is connected but the PMOD connector)

R3.2 cosmetic

Move LEDs and V-scoring a bit further back so the front panel doesn't tilt as much after being screwed on
Swap website out for apfelaudio.com
Remove solder deposits on text on bottom side (I think this was caused by a solder bath at the MFG)
Plate through holes on front panel

unsure if my eurorack pmod is running at all?

flashed my first firmware to an icebreaker ( with the caveat that i had to call iceprog explicitly ( see #43 ))

i think the flashing is successful?

$ iceprog build/icebreaker/top.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0xEF 0x40 0x18 0x00
file size: 104090
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
programming..
done.                 
reading..
VERIFY OK             
cdone: high
Bye.

but am just seeing -10V from the all outputs..

setup is the following

dixie -> mordax ( green trace, sine wave ) -> eurorack pmod input 1
eurorack pmod output 1 -> mordax ( blue trace, -10V)

VCO example seems broken after clocking rewrite

All the examples seem to work fine after switching to 48kHz all round and rewriting the clocking architecture -- except for the VCO example. It smells like a timing issue and this deserves investigation.

Actually this example still seems to work on the ECP5, it's only broken on ICE40