Comments (2)
Yes, will add a safeguard on full and agree in regards to making prog_full another possible interrupt_source, but this still needs to be solved in HW by some agreement/API at the end of the day.
(unless I am missing something).
Initial thought was to have one entry per core and then have dual sided communication whereby the host would send an ACK (through e_write) back to each core it received a message from. The core ID would be embedded in the message received by the host. The core would not be allowed to send another message until it has received an ACK from host that message has received.
So yes, having fifo full stopping writes is nice, but it doesn't solve the problem.
If we add pushback on fifo full, then yes we could keep pushing data, but if not properly used, this would flood the network quickly....will implement that now.
from oh.
implemented
from oh.
Related Issues (20)
- Publishing releases
- Potential glitch and failure possible in generic_fifo: combinational logic output passed to the other clock domain
- Error when building accelerator example HOT 1
- Open source Xilinx simulation models
- Consider using sphinx for nice documentation
- ELINK_VERSION platform field question HOT 1
- fpga for 7010 device may need reworking HOT 4
- RX: Dynamic mapping issues HOT 5
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- master branch parallella bitstreams broken
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