A framework to simplify the use of JESD204 with Analog Devices, Inc. data converters and clock chips.
Install JIF with pip
pip install --index-url https://test.pypi.org/simple/ pyadi-jif
Python interface and configurator for the ADI JESD204 Interface Framework
Home Page: https://analogdevicesinc.github.io/pyadi-jif/
License: Eclipse Public License 2.0
A framework to simplify the use of JESD204 with Analog Devices, Inc. data converters and clock chips.
Install JIF with pip
pip install --index-url https://test.pypi.org/simple/ pyadi-jif
Reclk of AD9081 must me >= 100 MHz
I think this only exists in the API
Core clocks (or device clock as we call it) must be always generated with the same source as the SYSREF.
They sample SYSREF so for deterministic latency we must ensure a fixed relation between the two.
The core clock/device clock must be always an integer submultiple of the sample clock, therefore we need the 8/12 scale in case of Nโ12 where we use the gearbox to translate from lane rate /66 (that is not a integer submultiple of the sample clock in this case) to device clock.
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