Nand2Tetris implemented in SystemVerilog intended to be used on an FPGA. This is mostly me playing around with Verilog and FPGAs so don't use this seriously.

This project uses Icarus Verilog for simulation and cocotb for verification.

Running make from the top-level directory should cause a build and all tests to run. After the initial build, tests will run incrementally on changed sources. make test can be used to always run all the tests.

Here is an assembly program running on an Elbert V2 dev board with a Xilinx Spartan 3A FPGA.

The 7-segment display is hooked up the to the D-register, and the CPU is clocked at 12 Hz.

Source Code:

start:
   // Initialize D to 9
   A := 9
   D = A
loop:
   D = D - 1
   A := @loop
   // If D is not zero, jump back up to loop
   D; jne

   // Jump back to start.
   A := @start
   0; jmp