A UART transceiver written in verilog. The individual transmitter and receiver modules are also included.
Module documentation is included in each module file.
uart.v
- UART serial transceiveruart_tx.v
- UART serial transmitteruart_rx.v
- UART serial receiver
/max_v_dev_kit
- Run the UART on the Max V development kit/test
- Test bench files/verilog
- Verilog source code