alfishe / 74xxx Goto Github PK
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License: MIT License
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tclaurentiu74xxx's Issues
74193 behaviour not correct
Regarding the 74193 behaviour, the Verilog model does not match the datasheet:
Line 265 in 4dbb7e8
In the datasheet, CLOCK_UP and CLOCK_DOWN rest high. However, in your implementation, if DOWN is toggled while UP is high, the counter counts up instead of down due to the else-if priority ordering.
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