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* Alessandro Di Chiara *
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This is a simple DLX processor with a 32-bit load/store architecture; it is totally implemented in VHDL.
Assembly programs are also provided, in order to test the processor. Machine code is generated by using
a Perl script (not implemented by me, so it is not provided, sorry). 
It has been developed as final project of a microelectronic course at the Politecnico di Torino 2015/16.
You can find more details into the Report.pdf file.