aleksandarkostovic / riscy-soc Goto Github PK

Hello, thank you in advance. I know it is unorthodox to ask questions such as this on the issues section of any repo.

I am a student hoping to use the CPU of this SoC for a research project. The project goal is to measure simulated power behavior with differing memory configurations, and the CPU's simplicity and memory I/O seemingly makes it a perfect fit. I came across some issues while trying to integrate it into my Xilinx Vivado project. My own misunderstanding of the code may be at fault, but I would appreciate any help getting things sorted out.
I started by cloning the repository, then adding cpu.v and all sub-module and file dependencies to the project. The first issue was that the module declarations in cpu.v caused errors, seemingly resolved by changing the form from "cpu_module_name module_name(...);" to "module_name cpu_module_name(...);"
At this point I attempted Vivado behavioral simulation and encountered several errors of form "concurrent assignment to a non-net 'variable_name' is not permitted. Errors like this occurred in cpu.v and several submodules, but was resolved by changing the variables from register types to wires.
Lastly I created a testbench file for the cpu module and began behavioral simulation proper. The instr_read_out signal was set to 1, but the instr_address_out wire was not set to anything. Nothing changed when I set a steady clock signal.
Have I fundamentally misunderstood something about how the CPU is meant to function? Can it work outside of its original context?

Thank you for your trouble.

Does this core runs Linux on it?

yosys -p 'synth_ice40 -top top -json top.json' top.v
....
....
....
2.2.1. Analyzing design hierarchy..
Top module: \top
Used module: \timer
Used module: \uart
Used module: \ram
Used module: \cpu
Used module: \bus_arbiter
Used module: \sync
ERROR: Module \cpu_mem' referenced in module \cpu' in cell `\mem' is not part of the design.