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License: MIT License
FPGA based blinky computer emulator
License: MIT License
RGB pins can only run in OD mode. This may work for column sink but not for controlling the row drivers.
Adafruit 1S LiPo cells use JST-PH connectors like this design, but the polarity is opposite of ours.
For next revision, either choose a different connector, or change polarity to match this semi-standard.
With the battery connector oriented the way it is, the leads from the battery drape over the ESP32 module antenna. Rotate the connector so this doesn't happen.
The large ground vias are too visible on the display side of the board. Replace with smaller vias, and double up if necessary.
In v1.0, the footprints for the CP2102N and FPGA seemed to have too much paste at the center, preventing the pins from soldering properly.
Fix by using packages without via slugs and with smaller paste apertures for the slugs. Or be more careful applying paste next time.
Programming the 8MByte flash with the CP2102N would take over a day at the ~2kHz SCK rate that flashrom generates.
The only clear solution is to move to a FT232H or FT2232H in the next rev
JLCPCB does a reasonable job of printing silk, but their process does not seem consistent from run to run as evidenced by minor gaps in some lines in v2.0 vs v1.0. Increase the line width for graphics and text to avoid this in the future.
Insure that vias stay clear of any silk on the 'front panel' back silk layer. Vias break up silkscreen, and can make the fine text on the front panel illegible. Seems to be done mostly well with V2.0, but back silk layer needs more thorough review for future revs.
The only violations of this are around the 'STATUS' legend under the status LED bank. This is an issue on both v1.0 and v2.0 PCBs.
Spacing between L/R buttons feels good. Move the 0/1 buttons apart to match.
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