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View Code? Open in Web Editor NEWI2C Master Verilog module
Home Page: http://www.circuitden.com/blog/21
License: GNU General Public License v3.0
I2C Master Verilog module
Home Page: http://www.circuitden.com/blog/21
License: GNU General Public License v3.0
I was using this module to write my own module to read some i2c device which has 16bit data.
It didn't work and then i came to the conclusion that there was a fault in the code.
So please fix this so in the future other people won't have to debug it.
Fault is in comments below:
S_WRITE_REG_DATA_MSB: begin
if (divider_tick) begin
case (process_counter)
0: begin
_serial_data = 1; // <----------------- Fault is here. It keeps the sda high 3 divider ticks (-;.
_process_counter = 1;
end
1: begin
//check for clock stretching
if (external_serial_clock == 1) begin
_last_acknowledge = 0;
_process_counter = 2;
end
end
2: begin
_serial_clock = 0;
_bit_counter = bit_counter - 1;
_process_counter = 3;
end
3: begin
if (bit_counter == 0) begin
_state = S_CHECK_ACK;
_post_state = S_WRITE_REG_DATA;
_post_serial_data = saved_mosi_data[7];
_bit_counter = 8;
_serial_data = 0;
end
else begin
_serial_data = saved_mosi_data[bit_counter+7];
end
_process_counter = 0;
end
endcase
end
end
Hi Sir,
I'm a student practicing verilog, I happen to see the I2C Verilog code which you have shared , I'm afraid that testbench had a bug and the FSM was not moving. I also see that the latest version of the testbench is in SystemVerilog, Can I please get the verilog version of the testbench for me to learn further.
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