The tlb-controller's discuss from 0mega28

tlb-controller's Issues

Parse USIMM traces

Just change the R to W and W to R.
Ignore the data part
The first column of the traces counts the number of non-load store instructions after which the current load/store operation is triggered, Simply ignore the 1st and last column in the trace.
Download source

std::string l_transactionStr = "";    std::string l_delimiter = " ";
    size_t l_pos = 0;
    std::string l_token;
    unsigned int l_count = 0;
    t_VirtualAddress l_address;
    t_RequestType l_reqType;
    t_Time l_traceTime;
    t_Size l_nonLsCount;
    t_Data l_data;
    while ((l_pos = l_transactionStr.find(l_delimiter)) != std::string::npos) {
        l_token = l_transactionStr.substr(0, l_pos);
        const char* l_value = l_token.c_str();
        char* l_end;
        if(l_count == 0)    {
            l_nonLsCount = strtol(l_value, &l_end, 0);
        }
        else if(l_count == 1)    {
            if(l_value[0] == 'W')   {
                l_reqType = t_RequestType::E_CORE_READ;
            }
            else if(l_value[0] == 'R') {
                l_reqType = t_RequestType::E_CORE_WRITE;
            }
            else        {
                assert(false);
            }
        }
        else if(l_count == 2)    {
            l_address = strtol(l_value, &l_end, 0);
        }
        else if(l_count == 3)    {
            l_data = new unsigned char[64];
            std::memcpy(l_data, l_value, 64);
        }
        l_transactionStr.erase(0, l_pos + l_delimiter.length());
        l_count++;
    }