Welcome to Verilator, the fastest Verilog/SystemVerilog simulator. Accepts synthesizable Verilog or SystemVerilog Performs lint code-quality checks Compiles into multithreaded C++, or SystemC Creates XML to front-end your own tools
	Fast Outperforms many commercial simulators Single- and multi-threaded output models
Widely Used Wide industry and academic deployment Out-of-the-box support from Arm, and RISC-V vendor IP
	Community Driven & Openly Licensed Guided by the CHIPS Alliance and Linux Foundation Open, and free as in both speech and beer More simulation for your verification budget
Commercial Support Available Commercial support contracts Design support contracts Enhancement contracts

Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code.

The user writes a little C++/SystemC wrapper file, which instantiates the "Verilated" model of the user's top level module. These C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator, or if you are looking for a behavioral Verilog simulator e.g. for a quick class project (we recommend Icarus Verilog for this.) However, if you are looking for a path to migrate SystemVerilog to C++ or SystemC, or your team is comfortable writing just a touch of C++ code, Verilator is the tool for you.

Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single-thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators).

Verilator has typically similar or better performance versus the closed-source Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar.

For more information:

• Verilator installation and package directory structure
• Verilator manual (HTML), or Verilator manual (PDF)
• Subscribe to verilator announcements
• Verilator forum
• Verilator issues

Verilator is a community project, guided by the CHIPS Alliance under the Linux Foundation.

We appreciate and welcome your contributions in whatever form; please see Contributing to Verilator. Thanks to our Contributors and Sponsors.

Verilator also supports and encourages commercial support models and organizations; please see Verilator Commercial Support.

• GTKwave - Waveform viewer for Verilator traces.
• Icarus Verilog - Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.

Verilator is Copyright 2003-2022 by Wilson Snyder. (Report bugs to Verilator Issues.)

Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details.