Processor-Design

Part - 1 (Individual Modules)

Aim

This assignment aims at designing ARM datapath modules and implementing these on the BASYS3 board. The following subset of ARM instructions has been chosen for implementation.

Arithmetic: <add|sub|rsb|adc|sbc|rsc> {cond} {s}
Logical: <and | orr | eor | bic> {cond} {s}
Test: <cmp | cmn | teq | tst> {cond}
Move: <mov | mvn> {cond} {s}
Branch: <b | bl> {cond}
Multiply: <mul | mla> {cond} {s}
Load/store: <ldr | str> {cond} {b | h | sb | sh }
cond: <EQ|NE|CS|CC|MI|PL|VS|VC|HI|LS|GE|LT|GT|LE|AL>

Instructions excluded are as follows:
Co-processor: cdp, mcr, mrc, ldc, stc
Branch and exchange: bx
Load/Store multiple: ldm, stm
Software interrupt: swi
Atomic swap: swp
PSR transfer: mrs, msr
Multiply long: mull, mlal

Instruction swi will be added later. Following are the building blocks :-

ALU

Inputs : two 32-bit operands, operation to be performed, carry
Outputs : 32-bit result of arithmetic/logical operation, next flag values

It is a combinational circuit that performs the arithmetic/logical operations for the DP instructions. The “operation to be performed” input can come from the opcode field of DP instructions. Its ability to add/subtract is also used by other instructions by giving appropriate inputs. This includes address offset addition/subtraction for DT and b|bl instructions as well as addition required in mla instruction. The ALU need not inherently know whether the addition it is doing is for add or ldr or bl or mla. Apart from the 32-bit result, the next values for the 4 flags are also output. Whether the flag values actually need to change is decided elsewhere.

Shifter

Inputs : 32-bit data to be shifted, shift type (LSL|LSR|ASR|ROR) and shift amount
Outputs : 32-bit data after shifting, shifter carry

It is a combinational circuit that performs the required shift operation by the specified number of bits. This serves the purpose for DP and DT instructions requiring shift. It also outputs shifter carry. Which carry (ALU or shifter) is to be used for updating the carry flag is decided elsewhere.

Multiplier

Inputs : Two 32-bit operands
Outputs : One 32-bit result

It is a combinational circuit that performs multiplication operation for mul and mla instructions. The addition required for mla instruction is done by ALU. For this assignment, a detailed design for multiplier is not required. Simply use multiply symbol in VHDL and leave the rest to the synthesizer.

Register File

Inputs : 32-bit data to be written, two 4-bit read addresses, one 4-bit write address, clock, reset, write enable
Outputs : two 32-bit data outputs, PC output

It has an array of sixteen 32-bit registers accessible through two read ports and one write port. It maintains a copy of register 15 out side the array for easy access as program counter. Clock and write enable have their usual meaning. Reset is used to initialize PC.

Processor-Memory Path

Inputs : 32-bit data from processor, 32-bit data from memory, type of DT instruction, byte offset in memory address
Outputs : 32-bit data to processor, 32-bit data to memory, memory write enable signals

It is a combinational circuit that provides byte manipulation and sign/zero extension needed for ldrb, ldrh, ldrsb, ldrsh, strb and strh instructions. For byte addressable memory, byte level write enable signals are required. These are also generated by this module.

Part - 2 (Instruction Set)

Overview

Datapath modules designed in week 6 are to be integrated to form the complete datapath. This will be a “multi-cycle” datapath, which means that it will allow instruction execution in multiple cycles. As opposed to a “single cycle” datapath, it provides for storage of temporary values computed at the end of intermediate cycles.

There are many ways in which the task of an instruction may be split into steps or micro- operations. What is proposed for this exercise is described below for various instruction groups. For DP and DT instructions Rn, Rd, Rs and Rm denote IR[19-16], IR[15-12], IR[11-8] and IR[3-0], respectively, where IR refers to the instruction. For multiply instructions Rn, Rd, Rs and Rm denote IR[15-12], IR[19-16], IR[11-8] and IR[3-0], respectively.

DP Group

1. Fetch instruction from memory, address given by PC. Add 4 to PC.
   
2. Read operand(s) from register file.
   a. Read operand1 from Rn for all instructions except for move sub-group
   b. Read operand2 from Rm, if it is not immediate type
   
3. Read shift amount from register Rs in register file, if it is specified by a register
   
4. Shift/rotate operand2, if required.
   
5. Perform DP operation. Set flags if required.
   
6. Write result into register Rd of register file, if it is not compare or test sub-group instruction.
   

DT Group

1. Fetch instruction from memory, address given by PC. Add 4 to PC.
   
2. Read base/offset from register file.
   a. Read base address from Rn in all cases
   b. Read offset from Rm, if it is specified by a register
   
3. Shift/rotate the offset, if required.
   
4. Add/subtract offset to base. In case of store instruction, read data from Rd of register file.
   
5. Perform memory read/write using address with/without offset (depending upon pre/post indexing). Write address (with offset) into register Rn of register file, if required.
   
6. Write the data read from memory into register Rd of register file in case of a load instruction.
   

Branch Group

1. Fetch instruction from memory, address given by PC. Add 4 to PC.
   
2. In case of BL instruction, write PC into lr register in register file. Add 4 to PC.
   
3. Add offset to PC.
   

Multiply Group

1. Fetch instruction from memory, address given by PC. Add 4 to PC.
   
2. Read multiplicands from Rn and Rs of register file.
   
3. Read addend from Rm of register file, if it is MLA instruction. Perform multiplication.
   
4. Perform addition, if it is MLA instruction.
   
5. Write result into register Rd of register file.
   

Notes

1. Actions shown in blue should be performed subject to the condition specified by IR[31-28] being satisfied.
   
2. The first step in all the instructions is common. It will help in simplifying controller design if the second step for all instructions is also made common (that is, always read from Rn and Rm, whether required or not). Then controller can look at the instruction type in step 2 and decide to follow different sequences for different cases from step 3 onwards.
   
3. The data path need not bother about sequencing of the steps or deciding whether a step is required or not. That is the job of the controller. In every cycle, the controller instructs the datapath to perform some step or micro-operations.
   

Part - 3 (Controller)

Aim

This note gives a brief description of various modules that constitute the controller for multi-cycle processor design of Lab assignment 5 (reference Lectures 12 and 13).

Instruction Decoder (Combinational)

It looks at the relevant instruction bits and determines the class, such as (DP | DT | MUL | B), sub-class such as (arith | logic | test) or (ldr | str | ldrh | strh | ldrb | strb | ldrsh | ldrsb), and variant, such as (imm | reg_imm | reg_reg) for the current instruction. It also indicates whether the instruction is implemented or unimplemented or undefined. The decoder needs to look at bits 27-20 and 11-4 of the instruction.

Flag check Unit or Bctrl Unit (Combinational)

It looks the four flags (V, C, Z, N) to determine if the condition specified by the instruction bits 31-28 is true or not. Note that if the condition field is “1111”, the instruction is undefined.

ALU control or Actrl (Combinational)

This is adequately described by slides 4 and 5 of Lecture 13.

Main Controller (Sequential)

This module may be divided into two parts in order to keep each part simpler.

Controller FSM (sequential)

This part includes control state register and the next state logic. A wide range of choices exists in defining the states. One extreme is to define enough states so the all control signals can be derived only from the control state in Moore style. The other extreme is to have only m states where m is the maximum number of cycles any instruction takes. Inputs to Controller FSM are those decoder outputs that influence state transitions. Output of the Controller FSM is the control state.

Control Signal Generator (Combinational)

Outputs of this module are the control signals. The inputs are control state and some decoder outputs. Depending upon how states are defined, this module may need to look at all the decoder outputs in one extreme scenario and may not look at any decoder output in the other extreme scenario. Some of the control signals need to be ANDed with Bctrl output and the signal enabling flag setting needs to be further ANDed with S bit of instruction.