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-_-_papers

ai-chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

alpr

AI course project - Automatic license plate recognition

aodnet-by-pytorch

Image Dehaze, Pytorch, An All-in-One Network for Dehazing, AOD-Net

arm7

Implemetation of pipelined ARM7TDMI processor in Verilog

arm9-compatible-soft-cpu-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

arm9tdmi

A softcore processor with ARM9TDMI architecture

awesome-deblurring

A curated list of resources for Image and Video Deblurring

benchmark_results

Visual Tracking Paper List

bp-neural-network-matlab

BP Neural Network in Matlab.

car-license-plate-recognition

Using Faster RCNN and KNN to perform Car License Plate Recognition

car-license-plate-recognition-1

基于tensorflow实现车牌照识别

catapult-v3-smartnic-re

Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

ccpd

[ECCV 2018] CCPD & PDRC: a diverse and well-annotated dataset for license plate detection and recognition

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cifar-10

Kaggle中的CIFAR-10原始图像分类问题，共有10类图片，训练集包含5万张图片。测试集包含30万张图片：其中有1万张图片用来计分，但为了防止人工标注测试集，里面另加了29万张不计分的图片。任务目标是对图片正确分类。

clpr.pytorch

End to End Chinese License Plate Recognition

cmsis_5

CMSIS Version 5 Development Repository

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

coursera-dl

Script for downloading Coursera.org videos and naming them.

coursera-ml-py

Python programming assignments for Machine Learning by Prof. Andrew Ng in Coursera

cs-notes

:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

cvpr16_deblur_study

A Comparative Study for Single Image Blind Deblurring (CVPR 2016)

dcpdn

Densely Connected Pyramid Dehazing Network (CVPR'2018)

ddr4-memory-controller

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

ddr4xmpeditor

Editor for DDR4 SPD and XMP