Output scaling factor about dblclockfft HOT 2 OPEN

The output scales at one additional bit for every two stages. This is based upon two principles:

1. Any incoming noise (zero mean, any standard deviation, any distribution) increases at a half a bit per stage. That is, the variance of the noise grows with the number of stages, but the standard deviation with the square root of the FFT length.
2. Any tones (i.e. non-zero mean) will increase in value at one bit per stage. That is, the mean output will at most be N times the mean input, where N is the FFT length.

Therefore, the FFT drops one bit every other stage. This minimizes the computational power required, at no loss of relevant precision.

Dan

from dblclockfft.

Hello Dan,
thanks for your explaination!

Following that logic, the output scale should be calculated according to 2 ^ (log2(FFT_LEN) / 2), right?
log2(FFT_LEN) to get the number of stages, and / 2 to account for the dropped bit in every other stage.

Now, if I understand the source code correctly, the first stage never drops a bit, so only the 3rd, 5th, etc.
This would lead to: 2 ^ ( (log2(FFT_LEN)-1) / 2) for the scale factor.

What is now still unclear to me, is the fact that is sometime "un-drops" a bit, according to the scale factors I found.
F=16, for example, has a scale factor of 1 (2^0), so it apparently never dropped a bit. But the generated Verilog actually shows, that the qtrstage drops a bit (input width == output width).

So I guess there is some other condition that affects the scale factor. Do you know what am I missing here?

Thanks and best regards,
Daniel

from dblclockfft.