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Zine.Chant's Projects

cacti icon cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

cuda_compression icon cuda_compression

A GPU-based LZSS compression algorithm, highly tuned for NVIDIA GPGPUs and for streaming data, leveraging the respective strengths of CPUs and GPUs together.

gem5 icon gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

ibex icon ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

llvm-project icon llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

models icon models

Models and examples built with TensorFlow

mqsim icon mqsim

MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)

nvcomp icon nvcomp

A library for fast lossless compression/decompression on the GPU

parda icon parda

fork of file_parda from bitbucket

simplessd icon simplessd

Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations

spark icon spark

Apache Spark - A unified analytics engine for large-scale data processing

truecell icon truecell

Employing TrueCells of DRAM for reliability.

xor_reduce icon xor_reduce

Repo for testing xorR operator in chisel3 with firrtl

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