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cnrv-fpu

Basic floating-point components for RISC-V processors

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

ece745

Verifiying a Wishbone to I2C Multiple Bus Controller using SystemVerilog

ece745_asicverification

Final Testbench for LC3 Microcontroller

ece745_lc3_verification

North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog

fpu

fpu_new

For CPU experiment

memory_verification_using_system_verilog

In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component

nyuziprocessor

GPGPU microprocessor architecture

openmips

A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

processor-uvm-verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-uvm-verification

seucourseshare

东南大学课程共享计划

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

uvm-core

vivado-on-silicon-mac

Installs Vivado on M1/M2 macs

z1