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amba_sys_ip

AMBA-protocol system IP

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

asynchronous_fifo

Design and Verification of Asynchronous FIFO

axi-bfm

AXI3 Bus Functional Models (Master & Slave)

cadence-git

Cadence Virtuoso Git Integration written in SKILL++

chatgpt-web

用 Express 和 Vue3 搭建的 ChatGPT 演示网页

chipyard

An Agile Chisel-Based SoC Design Framework

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

corsair

Control and Status Register map generator for HDL projects

drawio

drawio-desktop

Official electron build of diagrams.net

erasure-coding-accelerator

Erasure coding ASIC accelerator, implemented in system verilog.

fpga-sdcard-reader-spi

基于FPGA的 SD卡文件读取器，使用SPI总线，RTL实现,

lsfmonitor

A toop for LSF data-collection, data-analysis and information display.

notionnext

使用 NextJS + Notion API 实现的，支持多种部署方案的静态博客，无需服务器、零门槛搭建网站，为Notion和所有创作者设计。

pci-express-system-architecture---cn

本项目仅用于学习、研究用途，不得用于任何商业用途。如任何个人或机构将此翻译作品作商业用途使用，由使用人自行承担因此引发的一切法律责任，本项目组亦保留对其追究相关法律责任的权利。

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

rocket-linux-porting

scr1

SCR1 is an open-source RISC-V compatible MCU core

scr1_fpga

scr1_sp_tcm

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

swerv_sim

simulation env for swerv_th1, which is base on vcs & verdi

sync_fifo

Synchronous FIFO

tensorboard-cnn-visualization-example

Showing full TensorBoard support in Tensorflow for a CNN using MNIST data.

tensorflow

Computation using data flow graphs for scalable machine learning

veridian

A SystemVerilog Language Server

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.

verilog-ethernet

Verilog Ethernet components for FPGA implementation

weighted_round_robin

SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter