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aes128-hdl

A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.

cordic

An implementation of the CORDIC algorithm in Verilog.

cplusplusthings

C++那些事

dpu_on_zcu102

The Guidance For Installing dpu and some other stuff On Xilinx ZCU102

fpga_sm4

FPGA implementation of Chinese SM4 encryption algorithm.

hashcalculator

Helper tool to calculate hashes of data

kcfcpp

C++ Implementation of KCF Tracker

keras-yolo3

A Keras implementation of YOLOv3 (Tensorflow backend)

md5_core

MD5 core in verilog

modbus_crc_verilog

FPGA纯逻辑实现modbus通信

python-100-days

Python - 100天从新手到大师

resnet_py

Datasets, Transforms and Models specific to Computer Vision

sha2_pipelined

sha512

Verilog implementation of the SHA-512 hash function.

sm3_core

verilog-sha256

Implementation of the SHA256 Algorithm in Verilog

visual-tracking-development

Visual Object Tracking

vitis-ai

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

wang

DPU-Xilinx-log

xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

yolov3

YOLOv3 in PyTorch > ONNX > CoreML > TFLite

zynq

⚙️ 基于 Zynq-7 全可编程 SoC 的设计