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amba-ahb2apb-bridge-protocol

The Advanced Microcontroller Bus Architecture (AMBA) is an on-chip bus architecture used to Design high performance embedded microcontrollers and strengthen the reusability of IP core and widely used interconnection standard for system on chip (SOC). AMBA AHB (advanced high performance bus) is the highperformance bus means higher bandwidth or high clock frequency system modules. AMBA APB (advanced peripheral bus) as the name suggest used to connect peripheral to the architecture, peripherals like UART, Timer, keypad, PIO etc. this are part of low performance bus and it is optimized for low power consumption and interface reduced complexity to support peripheral functions. In this the functions of the AHB2APB Bridge to make the signals compatible with the high performance bus i.e. AHB with low performance bus i.e. APB, to do so we have to write the DUT code in Verilog and all other test case code in system Verilog, further have verified all the functions of bridge protocol using QuestaSim tool. The code coverage and functional coverage and functional verification of the Bridge RTL design is 97% covered by using QuestaSim

biriscv

32-bit Superscalar RISC-V CPU

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

core_jpeg

High throughput JPEG decoder in Verilog for FPGA

cores

Various HDL (Verilog) IP Cores

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

e200_opensource

The Ultra-Low Power RISC Core

fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

freedom

Source files for SiFive's Freedom platforms

hbird-e-sdk

The software development kit for Hummingbird E200 Series RISC-V Core and SoC platform

ic_system_design

Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.

yunhaifan Goto Github PK

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