yunhaifan Goto Github PK
Type: User
Type: User
The Advanced Microcontroller Bus Architecture (AMBA) is an on-chip bus architecture used to Design high performance embedded microcontrollers and strengthen the reusability of IP core and widely used interconnection standard for system on chip (SOC). AMBA AHB (advanced high performance bus) is the highperformance bus means higher bandwidth or high clock frequency system modules. AMBA APB (advanced peripheral bus) as the name suggest used to connect peripheral to the architecture, peripherals like UART, Timer, keypad, PIO etc. this are part of low performance bus and it is optimized for low power consumption and interface reduced complexity to support peripheral functions. In this the functions of the AHB2APB Bridge to make the signals compatible with the high performance bus i.e. AHB with low performance bus i.e. APB, to do so we have to write the DUT code in Verilog and all other test case code in system Verilog, further have verified all the functions of bridge protocol using QuestaSim tool. The code coverage and functional coverage and functional verification of the Bridge RTL design is 97% covered by using QuestaSim
32-bit Superscalar RISC-V CPU
Functional verification project for the CORE-V family of RISC-V cores.
High throughput JPEG decoder in Verilog for FPGA
Various HDL (Verilog) IP Cores
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
The Ultra-Low Power RISC Core
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Source files for SiFive's Freedom platforms
The software development kit for Hummingbird E200 Series RISC-V Core and SoC platform
Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
GNU toolchain for RISC-V, including GCC
Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
Wi-Fi LDPC codec Verilog IP core
ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU.
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.