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aladdin

A pre-RTL, power-performance model for fixed-function accelerators

andes-vector-riscv-dv

Andes Vector Extension support added to riscv-dv

ara-rv-vector-coprocessor

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

automatic-verilog

automatic-verilog based on vimscript

awesome-hdl

Hardware Description Languages

basic_verilog

Must-have verilog systemverilog modules

book-list-of-computational-geometry-and-computer-graphics

Book list of computational geometry and computer graphics 计算几何和计算机图形学必读书单与经典书籍

cores-swerv-eh2

gplgpu

GPL v3 2D/3D graphics engine in verilog

hdlgen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

hdlgen-chatgpt

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

hw

RTL, Cmodel, and testbench for NVDLA

kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

nyuziprocessor

GPGPU microprocessor architecture

open_regmodel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

systolic-array-implementation-in-rtl-for-tpu

IC implementation of Systolic Array for TPU

verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package