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aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-fpga

AES加密解密算法的Verilog实现

android2

《Android Studio开发实战：从零基础到App上线》随书源码（全面添加注释版）

androidserialport

Android串口通信示例

canadapter

A CANbus adapter for FPGA dev boards

dtcms

动力启航网站管理系统（简称DTcms），是目前国内ASP.NET开源界少见的优秀开源管理系统，基于 ASP.NET(C#)+ MSSQL(ACCESS) 的技术开发，全部100%免费开放源代码。

ip_stream_encryption_using_aes_and_fpga

This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a very optimized code for handling IP packets and encrypt/decrypt the data part using a 128-bit block cipher. It uses a pipeline and sub pipeline architecture.

litecan

FPGA-based lightweight CAN bus controller.

offlineswd

STM32系列离线烧写器

stm32_spi_sdcard

STM32 FatFS + SD Card Example via SPI interface

tinyaes