Comments (4)
First place to start would be the looking at the sys/arm.inc file. Copy that to a sys/riscv.inc and use it as a template for the RISC V.
Another question is we need 64bit RISC V unless there will be a lot of issues to address ! Was your fpga going to be 64bit ?
Create a riscv branch too for this to go in while it being worked on.
Would you be planning on having Linux or such on the fpga ? Or bare metal with ChrysaLisp direct on top ?
Chris
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The original plan was for 32bit but eventually 64 bit was planned so its just a slight reordering.
Initially bare metal as I dont want to add the other things that a linux kernel needs from the getgo.
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Yeah, 32bit does bring a lot of issue we can skip by having 64bit registers.
So eventually we will have to face the prospect of doing something with the main.c host interface for your FPGA. I'd say we first of all just go for getting the TUI stuff working after your happy with the RISC V backends code output.
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Happy to say this is now done. :)
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Related Issues (20)
- Fix Logging for new mail-box conventions HOT 1
- Transition Log Service to new IPC and data exchangers HOT 1
- Fix yaml string quote compounding
- Display scaling options? HOT 5
- src/main.cpp:37:11: fatal error: 'SDL.h' file not found HOT 5
- Package manager needed HOT 3
- @Chris HOT 16
- Containers woven in to foundations HOT 1
- Interprocess communication port needed HOT 4
- WYSIWYG interface builder HOT 6
- A browser for ChrysaLisp pages. HOT 10
- WebDriver compatible functional UI clicking test automation HOT 1
- reload definitions in lisp HOT 3
- error while compiling HOT 3
- error HOT 1
- rather a request: RISCV would be great HOT 10
- SDL2 dep for building on Macs - tweaks needed? HOT 9
- Bootstrapping ChrysaLisp on ChrysaLisp? HOT 10
- README feedback HOT 5
- Transparent windows HOT 1
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