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avsdadc_sky130

avsdbgp_3v3

avsdbdg_3v3 is a Bandgap Reference circuit, which is used to generate a constant voltage reference in analog domain which is independent of temperature and supply voltage variations.

avsdbgp_3v3_sky130_v1

avsdbgp_3v3_sky130_v2

avsdcmp_3v3_sky130

avsddac_3v3

avsddac_3v3_sky130_v1

avsddac_3v3_sky130_v2

avsdmux2x1_3v3

avsdmux4x1_3v3

avsdpll_1v8_sky130_ss

risc-v-myth-workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

rvmyth_avsddac_interface

rvmyth_avsdpll_interface

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

vsd-iat-workshop-github-repos

GitHub is the new Resume for VLSI industry GitHub is indeed the new RESUME for VLSI industry. Really, if you are recruiting person and looking forward to judge a new candidate for a role in company, ask for GitHub project link. Projects written on resume and projects available on GitHub by a candidate will immediately give you an idea about his/her perseverance, dedication, sincerity, productivity and amount of hard-work he/she can put inside a project.

vsdbabysoc

vsdbbcud4f

vsdcontainer

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

vsdmemsoc

vsdmixedsignalflow

This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

vsdopen2021_bgr

vsdospowercalc

vsdscl180

vsdsquadron

vsdsquadron_pio

vsdsquadronpro

vsdsram

An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.

vsdsram_sky130