Comments (4)
Hi @Nikhil-311293,
this error indicates that the width of the VLSU's operands does not match the width of Vicuna's memory interface. In your configuration file the width of the VLSU is configured to 32 bits, hence the memory interface must also be 32 bits wide. Unfortunately Vivado does not print the full error message, thus I cannot see which value you have provided for the memory interface width.
The width of Vicuna's memory interface is controlled by the parameter XIF_MEM_W
of the vproc_core
module or the parameter VMEM_W
of the vproc_top
module. Set either of these parameters to 32 and you should no longer get that error.
from vicuna.
With your suggestions now I'm able to synthesize the vicuna vector coprocessor for Genesys2 board using Ibex core.
Thank you for your time.
Now I'll have to implement the design and generate the bitstream for the same.
I wanted to ask this one thing, can I port the same design for other Xilinx FPGA e.g. VCU118 ultrascale FPGA?
from vicuna.
Hi @Nikhil-311293,
yes, the design should be portable between Xilinx FPGAs. I am unsure if the primitives used by the ultrascale FGPAs are the same as those used by the 7 series FPGAs, so there might some adaptions required, but these should be rather straightforward.
Have a look at the README in the demo
subdirectory, that gives some instructions on how to add another board.
from vicuna.
After being able to successfully synthesize the vicuna coprocessor for Xilinx's Virtex Ultrascale FPGA, now I'm trying to implement the design and generate the bitstream for it.
My ultimate aim is boot Linux on it run few simple example programs on it. The problem I'm getting now is: referring as you suggested about the demo and sw subdirectory ---->
Do I need to put constraints for mem_req_o, mem_addr_o, mem_wdata_o etc ports which are declared in the top module vproc_top.sv??
or Do I need to initialize the MIG IP from Xilinx to serve this purpose?
As the constraints used in demo subdirectory are exclusively for UART test program, I believe.
I've attached screenshot below to illustrate this. How shall I move ahead in this particular task? Your suggestions will be extremely useful in this further progress.
Thank you in advance.
from vicuna.
Related Issues (20)
- Vicuna accepts instructions for which source registers are not valid.
- Wrong result generated by multiply unit (probably control logic related) HOT 1
- Wrong operand for `vwmacc(u|us|su).vx`
- narrowing instructions are never popped from the instruction queue HOT 1
- Vicuna + Ibex and WFI
- No way to clear a cache error?
- fail to set VREG_W=2048 HOT 2
- Floating point support.
- Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
- 'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
- Error in Questasim Simulation
- Reserved word not implemented: 'config' HOT 1
- Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model HOT 1
- Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely
- Signal stability issue on result interface HOT 4
- Suggestion for vectorizing MaxPool and Convolution Layer HOT 1
- Rounding issue for `vasub(u).(vv|vx)`
- Tail-undisturbed policy violation for comparison instructions.
- Masking not working
- `vslidedown.(vx|vi)` issue when VLMAX is exceeded
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