This might not be immediately actionable but can we have and DSL which describes the p

In some way, the current mapping deion is already kind of DSL implemented on the

Automated Meta Code Generation of MIR Code and Infrastructure about mir HOT 1 OPEN

vnmakarov commented on May 6, 2024

Automated Meta Code Generation of MIR Code and Infrastructure

from mir.

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vnmakarov commented on May 6, 2024 2

In some way, the current mapping description is already kind of DSL implemented on the top of C:

mir/mir-gen-x86_64.c

Lines 725 to 779 in ced7620

 struct pattern { 

 MIR_insn_code_t code; 

 /* Pattern elements: 

  blank - ignore 

  X - match everything 

  $ - finish successfully matching 

  r - register (we don't care about bp and sp because they are fixed and used correctly) 

  h[0-31] - hard register with given number 

  z - operand is zero 

  i[0-3] - immediate of size 8,16,32,64-bits 

  p[0-3] - reference 

  s - immediate 1, 2, 4, or 8 (scale) 

  m[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits 

  ms[0-3] - signed int type memory of size 8,16,32,64-bits 

  mu[0-3] - unsigned int type memory of size 8,16,32,64-bits 

  mf - memory of float 

  md - memory of double 

  mld - memory of long double 

  l - label which can be present by 32-bit 

  [0-9] - an operand matching n-th operand (n should be less than given operand number) 

  Remmeber we have no float or (long) double immediate at this stage. They are represented by 

  a reference to data item. */ 

 const char *pattern; 

 /* Replacement elements: 

  blank - ignore 

  ; - insn separation 

  X - REX byte with W=1 

  Y - Optional REX byte with W=0 

  Z - Obligatory REX byte with W=0 

  [0-9A-F]+ pairs of hexidecimal digits opcode 

  r[0-2] = n-th operand in ModRM:reg 

  R[0-2] = n-th operand in ModRM:rm with mod == 3 

  m[0-2] = n-th operand is mem 

  mt = temp memory in red zone (-16(sp)) 

  mT = switch table memory (h11,r,8) 

  ap = 2 and 3 operand forms address by plus (1st reg to base, 2nd reg to index, disp to disp) 

  am = 2 and 3 operand forms address by mult (1st reg to index and mult const to scale) 

  ad<value> - forms address: 1th operand is base reg and <value> is displacement 

  i[0-2] - n-th operand in byte immediate (should be imm of type i8) 

  I[0-2] - n-th operand in 4 byte immediate (should be imm of type i32) 

  J[0-2] - n-th operand in 8 byte immediate 

  P[0-2] - n-th operand in 8 byte address 

  T - absolute 8-byte switch table address 

  l[0-2] - n-th operand-label in 32-bit 

  /[0-7] - opmod with given value (reg of MOD-RM) 

  +[0-2] - lower 3-bit part of opcode used for n-th reg operand 

  c<value> - address of 32-bit or 64-bit constant in memory pool (we keep always 64-bit 

  in memory pool. x86_64 is LE) 

  h<one or two hex digits> - hardware register with given number in reg of ModRM:reg; 

  one bit of 8-15 in REX.R 

  H<one or two hex digits> - hardware register with given number in rm of MOD-RM with and mod=3 

  (register); one bit of 8-15 in REX.B v<value> - 8-bit immediate with given hex value V<value> - 

  32-bit immediate with given hex value 

  */

For example, binutils is using even more primitive approach based on C macros and binutils supports much more architectures than one.

To create a general DSL to describe insns (and MIR mapping) of existing processors is a pretty big job. Architectures are so different.

I know one attempt https://sourceware.org/cgen written by one my former colleague. I would not say that its description is more understandable. It failed to be used by binutils, gcc, gdb, simulators etc.

So I prefer a natural approach, informal MIR insn defs in MIR.md and approach currently used by x86_64 mir generator. As I add more architectures, I may be will see that I need implementation of more general DSL.

from mir.

Automated Meta Code Generation of MIR Code and Infrastructure about mir HOT 1 OPEN

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	struct pattern {
	MIR_insn_code_t code;
	/* Pattern elements:
	blank - ignore
	X - match everything
	$ - finish successfully matching
	r - register (we don't care about bp and sp because they are fixed and used correctly)
	h[0-31] - hard register with given number
	z - operand is zero
	i[0-3] - immediate of size 8,16,32,64-bits
	p[0-3] - reference
	s - immediate 1, 2, 4, or 8 (scale)
	m[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits
	ms[0-3] - signed int type memory of size 8,16,32,64-bits
	mu[0-3] - unsigned int type memory of size 8,16,32,64-bits
	mf - memory of float
	md - memory of double
	mld - memory of long double
	l - label which can be present by 32-bit
	[0-9] - an operand matching n-th operand (n should be less than given operand number)

	Remmeber we have no float or (long) double immediate at this stage. They are represented by
	a reference to data item. */
	const char *pattern;
	/* Replacement elements:
	blank - ignore
	; - insn separation
	X - REX byte with W=1
	Y - Optional REX byte with W=0
	Z - Obligatory REX byte with W=0
	[0-9A-F]+ pairs of hexidecimal digits opcode
	r[0-2] = n-th operand in ModRM:reg
	R[0-2] = n-th operand in ModRM:rm with mod == 3
	m[0-2] = n-th operand is mem
	mt = temp memory in red zone (-16(sp))
	mT = switch table memory (h11,r,8)
	ap = 2 and 3 operand forms address by plus (1st reg to base, 2nd reg to index, disp to disp)
	am = 2 and 3 operand forms address by mult (1st reg to index and mult const to scale)
	ad<value> - forms address: 1th operand is base reg and <value> is displacement
	i[0-2] - n-th operand in byte immediate (should be imm of type i8)
	I[0-2] - n-th operand in 4 byte immediate (should be imm of type i32)
	J[0-2] - n-th operand in 8 byte immediate
	P[0-2] - n-th operand in 8 byte address
	T - absolute 8-byte switch table address
	l[0-2] - n-th operand-label in 32-bit
	/[0-7] - opmod with given value (reg of MOD-RM)
	+[0-2] - lower 3-bit part of opcode used for n-th reg operand
	c<value> - address of 32-bit or 64-bit constant in memory pool (we keep always 64-bit
	in memory pool. x86_64 is LE)
	h<one or two hex digits> - hardware register with given number in reg of ModRM:reg;
	one bit of 8-15 in REX.R
	H<one or two hex digits> - hardware register with given number in rm of MOD-RM with and mod=3
	(register); one bit of 8-15 in REX.B v<value> - 8-bit immediate with given hex value V<value> -
	32-bit immediate with given hex value
	*/