Verilog vs liberty output mismatch about openram HOT 24 CLOSED

Thanks, we are aware of this issue and it will be fixed in an upcoming release very soon.

We have separated the data bus into separate din and dout ports so the OEb is no longer necessary but was not removed from the verilog.

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Excellent, thank you! So I'll simply remove this OEb port from my verilog.

Another issue is related. Yosys fails to parse the liberty output in current format:
pin(DOUT0[63:0]){ ... }

My workaround is to remove brackets [63:0] and leave pin (DOUT0) {...}. Please remove this from your scripts as well

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Thank you. Waiting forward working with your next release. Any contributions required ?

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@mguthaus Yosys parses the *.lib files if you remove bus widths from pin descriptions :
pin(DOUT0[63:0]){ ... } -> pin(DOUT0){ ... }

I also made a verilog wrapper for your memories to match lib files. I was able to synthesize it with an updated lib file in Yosys.

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Pls leave your comment here too: https://www.reddit.com/r/yosys/comments/a4ovm6/liberty_syntax_support/

I'm working with Tim now. No problems in qflow with that. I don't have access to commercial tools, so pls check on your own or give me access to your tools for test purposes.

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I confirm that updated *.lib file works seamlessly with opensta. Synthesized, checked.
Please, follow my feedback and remove bus width in the next release.

Here's my wrapper for your SRAM. Feel free to update your verilog output as well

Thank you!

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from openram.

I synthesized your SRAM with my verilog wrapper and run the opensta script to obtain timing report. I used OSU035 with a 10ns clock, which yielded in a 9.86ns slack. Do you want to get my scripts ?

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If you think it is the Yosys issue, pls feel free to open a RFC for this in the Yosys repo. If you want to double check my scripts, let me know. I'll share

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Pls check here

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Any follow up questions? Should I close this issue ?

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from openram.

Happy New Year! Any news?

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Sounds great. Let me know if I can contribute in this project. I can do testing, validation, integration and verification, since I use your stuff in my commercial project.

If you have an idea, let me know

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I finally got to trying this out in Library Compiler and it fails without these bus notations.

Reading '/home/mrg/OpenRAMLibrary/deliverables/freepdk45/2019-02-21/sram_8b_512_1rw_freepdk45/sram_8b_512_1rw_freepdk45_TT_1p0V_25C.lib' ...
Error: Line 96, Cell 'sram_8b_512_1rw_freepdk45', bus 'DIN0', Invalid bus syntax is detected in 'DIN0'. (LBDB-176)
Error: Line 135, Cell 'sram_8b_512_1rw_freepdk45', bus 'DOUT0', Invalid bus syntax is detected in 'DOUT0'. (LBDB-176)
Error: Line 169, Cell 'sram_8b_512_1rw_freepdk45', bus 'ADDR0', Invalid bus syntax is detected in 'ADDR0'. (LBDB-176)

Unfortunately, I will need to add them back and we should fix Yosys.

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This issue was coincidentally opened 4 hours ago for Yosys:
YosysHQ/yosys#825

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