Feature: dual port SAM (sequential access memory) about openram HOT 3 CLOSED

Thanks for the feature request. This is a great suggestion and I appreciate you taking the time to post this. We will keep this open while we can get to it.

We are in the process of a major rewrite to fix some power supply organization and other issues that will let us scale to newer technologies (7nm, 14nm) and multiport more easily. These are taking priority for now.

from openram.

The SAM article I was referring to is from 2002:
Low-Power Sequential Access Memory Design
Joong-Seok Moon, William C. Athas, Peter A. Beerel, Jeffrey T. Draper
https://www.isi.edu/~draper/papers/cicc02.pdf

Apparently there is a patent from 2004 owned by Aptina (now ON semi), strangely I did not know about it. I will not provide links and there obviously is some prior art.

In a SAM, even if replacing the address controller with a one hot shift register does not save much area, there is no need to wire the address bus from a state machine to the memory, this should improve timing. Address counters are generally still needed, to prevent underflow/overflow, but there is no need to connect them to the memory.

The other topic was pseudo static RAM. This is DRAM with a SRAM like interface, a controller handling refresh and similar hides most of the overhead.
https://en.wikipedia.org/wiki/1T-SRAM
https://en.wikipedia.org/wiki/Dynamic_random-access_memory#PSRAM
As I mentioned there are use cases where DRAM data retention is not an issue, since data is overwritten at a higher rate then the refresh cycle. While some dedicated DRAM circuitry might still be needed (I am not an expert), it should be possible to avoid the area overhead of a refresh circuit and SRAM cache. While searching a few years ago I was unable to find a PSRAM without controller overhead. The overhead might not seem much for a single large memory (CPU data), but is significant if many small independent memories are needed (FIR, FIFO, ... buffers in a complex pipeline).

from openram.

We would accept this as a contribution but it is not on the roadmap.

from openram.