User-defined attributes not supported about rust_hdl HOT 2 CLOSED

entity sample1 is
  port (
    CLK : in std_logic;
    nCLK : out std_logic
  );
end entity;

architecture a of sample1 is

  --From numeric_std.vhd line:1302
  function "abs" (ARG: SIGNED) return SIGNED is
    constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
    alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
    variable RESULT: SIGNED(ARG_LEFT downto 0);
    -- Exemplar synthesis directives :
    attribute IS_SIGNED of ARG:constant is TRUE ;
    attribute SYNTHESIS_RETURN of RESULT:variable is "ABS" ;
  begin
    if ARG'LENGTH < 1 then return NAS;
    end if;
    RESULT := TO_01(XARG, 'X');
    if (RESULT(RESULT'LEFT)='X') then return RESULT;
    end if;
    if RESULT(RESULT'LEFT) = '1' then
      RESULT := -RESULT;
    end if;
    return RESULT;
  end "abs";
  
  --From std_logic_1164.vhd:42
  TYPE std_ulogic IS ( 'U',  -- Uninitialized
                       'X',  -- Forcing  Unknown
                       '0',  -- Forcing  0
                       '1',  -- Forcing  1
                       'Z',  -- High Impedance   
                       'W',  -- Weak     Unknown
                       'L',  -- Weak     0       
                       'H',  -- Weak     1       
                       '-'   -- Don't care
                      );

     ATTRIBUTE logic_type_encoding : string ;
     ATTRIBUTE logic_type_encoding of std_ulogic:type is
                     ('X','X','0','1','Z','X','0','1','X') ;

  component sample2 is
    port (
      CLK : in std_logic;
      nCLK : out std_logic
    );
  end component sample2;

  attribute BOX_TYPE : string;
  attribute BOX_TYPE of sample2 : component is "user_black_box";

begin

  Inst_sample2 : sample2
    port map	(
      CLK <= CLK,
      nCLK <= nCLK
    );
end a;

entity sample2 is
  port (
    CLK : in std_logic;
    nCLK : out std_logic
  );
end entity;

architecture a of sample2 is
  signal s_nclk : std_logic;
begin

  s_nclk <= not CLK;
  nCLK <= s_nclk;

end a;