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arch_test-danish

beaglevv

beaglev

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.

fp_division

SystemVerilog based IEEE-754 Floating Point Division Algorithm which is direct translation of the C source file, part of the SoftFloat IEEE Floating-Point Arithmetic Package, Release 3d, by John R. Hauser.

fpu_division

SystemVerilog based IEEE-754 Floating Point Division Algorithm. It is synthesizable functional block of FPU divide unit tested and verified on Mentor Questa 2021.3.

gem5

Fork of main gem5 repo: https://gem5.googlesource.com/public/gem5/

gem5-bootcamp-env

introduction-to-soc-design-education-kit

Introduction to SoC Design Education Kit

matmul_accelerator

rapid-embedded-education-kit

Rapid Embedded System Education kit

riscv-arch-test

riscv-hackathon

Tools Installation guide for RISC-V Hackathon

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-tests-vector

riscv-validation

Scripts/tests/configurations needed for configuring a real RISC-V board in gem5 live here

sail-riscv

Sail RISC-V model

simple-django-project

A simple Django project which uses MySQL as database. It has Signup, Login, Logout functionality. It lets you search for countries, cities, languages from the default mysql dump. Django's user table has been overridden to store user information.