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Tyler McGrew's Projects

avl-tree icon avl-tree

A Java implementation of an AVL self-balancing binary search tree that stores key-value pairs

mips-processor-verilog icon mips-processor-verilog

A processor which implements a subset of the MIPS Instruction Set Architecture, written in Verilog for an Altera FPGA

quartus_verilog_builder icon quartus_verilog_builder

Tool to compile user-input settings from an XML file into a verilog header file and a csv pin assignments file

risc-v icon risc-v

An implementation of the RISC-V 32I ISA on an Altera FPGA in Verilog with a cache and process-switching OS

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