Comments (7)
I tried making these changes
diff --git a/trace/CacheTest.cpp b/trace/CacheTest.cpp
index e5d1846..86dea1b 100644
--- a/trace/CacheTest.cpp
+++ b/trace/CacheTest.cpp
@@ -11,9 +11,9 @@ CacheTest::CacheTest()
void CacheTest::runTest()
{
- cacheParameters p = cacheParameters(0, 64, "L1", 8 * 512, 1, 5, 1);
- cacheParameters p2 = cacheParameters(1, 64, "L2", 8 * 64 * 1024, 1, 10, 6);
- cacheParameters p3 = cacheParameters(2, 64, "L3", 8 * 1024 * 1024, 1, 15, 11);
+ cacheParameters p = cacheParameters(0, 64, "L1", 8 * 512, 2, 5, 1);
+ cacheParameters p2 = cacheParameters(1, 64, "L2", 8 * 64 * 1024, 2, 10, 6);
+ cacheParameters p3 = cacheParameters(2, 64, "L3", 8 * 1024 * 1024, 2, 15, 11);
Wouldn't that make each cache 2-way associative?
This doesn't create any exceptions for me. Were you using a non-power-of-2 N?
from cache-simulator.
Oh nevermind... I do get a seg fault on a bigger trace file, but only for N = 4, not N = 2
from cache-simulator.
==27229==
==27229== Invalid write of size 4
==27229== at 0x401362: address::operator==(address const&) (Address.cc:40)
==27229== by 0x40625F: cacheBlock::inBlock(address) (CacheBlock.cc:40)
==27229== by 0x406545: cacheSet::inCacheSet(address) (CacheSet.cc:59)
==27229== by 0x4017A7: cache::hasAddress(address) (Cache.cc:63)
==27229== by 0x403DFB: cacheArchitecture::cacheRead(address) (CacheArchitecture.cc:52)
==27229== by 0x40715D: CacheTest::runTest() (CacheTest.cpp:32)
==27229== by 0x407491: main (main.cpp:6)
==27229== Address 0x0 is not stack'd, malloc'd or (recently) free'd
==27229==
==27229==
==27229== Process terminating with default action of signal 11 (SIGSEGV)
==27229== Access not within mapped region at address 0x0
==27229== at 0x401362: address::operator==(address const&) (Address.cc:40)
==27229== by 0x40625F: cacheBlock::inBlock(address) (CacheBlock.cc:40)
==27229== by 0x406545: cacheSet::inCacheSet(address) (CacheSet.cc:59)
==27229== by 0x4017A7: cache::hasAddress(address) (Cache.cc:63)
==27229== by 0x403DFB: cacheArchitecture::cacheRead(address) (CacheArchitecture.cc:52)
==27229== by 0x40715D: CacheTest::runTest() (CacheTest.cpp:32)
==27229== by 0x407491: main (main.cpp:6)
from cache-simulator.
This is pretty suspicious...
CacheSet::inCacheSet(address) (CacheSet.cc:59)
in = blocks[i].inBlock(address(add.getAddr() >> (int)log(blockSize)));
What's that supposed to do?
I'm guessing it's at least supposed to be log2 and not log?
Also, why create a weird address like that?
from cache-simulator.
that is so that the cache always ignores the byte select bits of the addresses it receives. While we will typically read 32 bit words from cache blocks, our block size typically exceeds the 32 bit word size, so if two contiguous 32 bit words are present in a cache block one with the address of 128 and the other with address 127, the intent of that code is to strip off the byte select portion of the address to realize that they map to the same place and are both available.
Also it should probably be log2
from cache-simulator.
OK so you are creating a new address that is just the tag and not the full address?
That might be a good place to think about using a getTag() function on the address
from cache-simulator.
Fixed this bug. The earlier code was misusing the associativity in a way that would potentially cause a reference to a non-existent set
from cache-simulator.
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from cache-simulator.