tklam Goto Github PK

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

asr-server

FastCGI support for Kaldi ASR

birdie

A Vim plugin that facilitates Verilog netlist tracing

chisel-template

A template project for beginning new Chisel work

deletefb

Automate Scrubbing your Facebook Presence

doc-cam

emokit

Open source driver for accessing raw data from the Emotiv EPOC EEG headset

from-me-to-you

google-map-traffic-analysis

Try to analyse the traffic conditions of a region on Google Map

hands-on-python-machine-learning

Hands-on Introduction to Python And Machine Learning

horsekell

Web scraper to download Hong Kong's horse racing data

infinitime

Firmware for Pinetime smartwatch written in C++ and based on FreeRTOS

irstlm

just-a-telegram-bot-example

kissnn

licensing-server

linux-commands-for-beginners

Linux commands for beginners

magia

Magia generates Synthesizable SystemVerilog in pythonic syntax in a simple and intuitive way

monero

Monero: the secure, private, untraceable cryptocurrency

opencamera

opencc

A project for conversion between Traditional and Simplified Chinese

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

see

See is a Qt/QML+OpenCV application for mobile phones (Android/iOS) to determine the colour of an object.

shattered-pixel-dungeon

Traditional roguelike game with pixel-art graphics and simple interface

software-requirements-specification

This repository holds a Software Requirements Specification document written in Markdown, specifically tailored for Github users. The original document that inspired this work states that the document is "Copyright © 1999 by Karl E. Wiegers. Permission is granted to use, modify, and distribute this document." (From http://www.frontiernet.net/~kwiegers/process_assets/srs_template.doc)

telepot

Python framework for Telegram Bot API

trading-market

veetootee

verilator

Verilator open-source SystemVerilog simulator and lint system

video-summary

Yet another proof-of-concept...