Compatibility of SF 5,6 with sx1261/2 about gr-lora_sdr HOT 8 CLOSED

Sure, it's described at page 36 of https://semtech.my.salesforce.com/sfc/p/E0000000JelG/a/3n000000qOUu/tpcW.qidS7dE9fxMVN_v5okCY64Xiq5OUeNNFal1a8c

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You can check this report on the reverse engineering of the rest of the physical layer to give you some hints on how you can proceed. And this nice presentation.
I would be happy to accept a pull request if you add this capability!

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Hi @jduses,
for chips other than the SX1261/2, the datasheets indicates that the explicit header mode can't be used for SF<7.
This makes sense because the explicit header consists in 20 bits, which need to fit within the first 8 LoRa symbols sent with CR=4/8 and low datarate optimization, which exactly gives 20 bits for SF7.
To enable the explicit header for SF 5 and 6, they may have done many things (e.g. defining a different header structure, sent more symbols with CR 4/8 and LDRO, disable LDRO,...). I however didn't had the time to reverse engineer this for those chips yet.

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Does this problem exists for SX1268 too?

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Hi @nkaramolegos,
based on the datasheets, there will be the same issue for sf5 and 6. I'll add this to the readme

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Can you send me the reference? Thanks

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Do you have any hints on how to reverse engineer these chips?

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Hi,
as there is no real question pending I will close this issue for now, but don't hesitate to reopen it if needed

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