Related Issues (20)
- Qsysify and Axi4: incorrect _hw.tcl generation HOT 1
- Could not load XSI simulation shared library HOT 1
- Blackboxing RAM with one read and one readWrite port HOT 2
- Performance of PriorityMux HOT 18
- Redundant Flow API Calls. HOT 4
- Parallel test execution in SpinalSim? HOT 5
- Are there some bugs in clockDomain.waitSampling() API? HOT 10
- Is there a "DONT_TOUCH" attribute for Components in Spinal ? HOT 2
- Unknown reason for hierarchy violation HOT 4
- Slower on the intranet network HOT 9
- Support for memories with read latency higher than 1 HOT 18
- Can't infer width of Payload HOT 5
- Seed does not work at parallel test of spinal sim HOT 4
- Underscore in literals HOT 5
- Linux: Spaces in path break formal verification HOT 7
- new condtion syntactic suga HOT 6
- `privateNamespace` changes BlackBox component name HOT 1
- 『Help』Component Interface Name Changes Result in SpinalHDL Generating Excessive Redundant Module.v Files. HOT 4
- Register fields with AccessType ROV don't get names
- When’ Requirement: Merging ‘setWhen’ and ‘clearWhen’ in Verilog Output HOT 2
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