Name: Sidhant priyadarshi
Type: User
Company: KLE Technological University
Bio: Hey Folk's,
I am Sidhant Priyadarshi working as a Senior GPU Design Verification Engineer at Samsung.
Location: bihar
Blog: linkedin.com/in/sidhant-priyadarshi-028612185/
Sidhant priyadarshi's Projects
4 bit divider design using first divider algorithm
4 request first come first serve arbiter design using verilog HDL
verilog design of first multiplier design and architecture
Lab projects using Verilog HDL
Advanced Pheripheral Bus design using verilog HDL
2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology
Here i designed a converter circuit which converts analog sine signal to digital clock signal.This is my personal work which suddenly came into my mind so i designed.I used half wave rectifier circuit with filter to get +ve half of sine wave and then used comparator to convert that into square wave which is digital clock output.
basic projects using python
verilog code to covert binary number into canonical signed digit(csd)
csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.
designed simple digital circuits using verilog
designed a simple D-flipflop from JK-flipflop using eSIM and SKY130nm pdk
Design and verification of first come first serve arbiter
learning python
practicing 2020 google kickstart questions using python
i have designed a beautiful guess game using python. Lerning python part3
IEEE-latex-report for 32-bit CSD multiplier
lottery game using python
learning opencv basics
designed simple digital circuits using pipeline
PWM module using verilig HDL in XILINX ISE
Contains my resume
Design of real time clock(RTC) using Verilog HDL
I worked personally on designing rv32i processor for some of the instructions like add,addi,sub,etc..
Config files for my GitHub profile.
social distance maintainer using arduino uno R3
basic problem statements and solution of machine learning
TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board