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80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

alice5

SPIR-V fragment shader GPU core based on RISC-V

atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

cachesim

A simple cache simulator

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs

eve_ide

eveide_light

A lightweight IDE that supports verilog simulation and Risc-V code compilation

flexpret

glide

3Dfx Glide -- forked from CVS repository at https://sourceforge.net/projects/glide/

gplgpu

GPL v3 2D/3D graphics engine in verilog

hga101_gpu

nyuziprocessor

GPGPU microprocessor architecture

openfpga

An Open-source FPGA IP Generator

pvs32_soc

Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus

pvs332

Pan's SoC Gen 2, multicycle RV32ia

pvs464

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

sm3_core

soc_automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

tinygl

TinyGL : a Small, Free and Fast Subset of OpenGL*

uvm

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

uvmreference

Reference examples and short projects using UVM Methodology

vortex