work around Cortex-M7 BASEPRI erratum about rtic HOT 2 CLOSED

Is there a reason why the heavy handed sequence of disable interrupts, raise execution priority, enable interrupts is required? according to errata 837070 documented on page 14 of Cortex-M7 (AT610) and Cortex-M7 with FPU (AT611) Software Developer Errata Notice (Version 9.0 issued on 04-Dec-2019) only the instruction directly following the msr BASEPRI/BASEPRI_MAX are still potentially executed with the old priority on Cortex M7 r0p1 cores. Isn't it enough to always schedule a single nop directly after the msr?

from rtic.

I haven't looked closely into this, but the gut feeling is that it should work with a NOP following the BASEPRI related instruction. The assembly instructions should be executed in "program order" (not being allowed for the compiler to re-order).

from rtic.