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asl-interpreter

Example implementation of Arm's Architecture Specification Language (ASL)

berkeley-softfloat-3

SoftFloat release 3

berkeley-testfloat-3

TestFloat release 3

buildroot

cannoli

High-performance QEMU memory and instruction tracing

capstone

Mirror of git://qemu.org/capstone.git

ck

Concurrency primitives, safe memory reclamation mechanisms and non-blocking (including lock-free) data structures designed to aid in the research, design and implementation of high performance concurrent systems.

dtc

Mirror of git.qemu.org/dtc.git

hellosilicon

An introduction to ARM64 assembly on Apple Silicon Macs

kae

A high-performance hardware acceleration algorithm library of OpenSSL engine based on Kunpeng processor

keycodemapdb

Mirror of git://qemu.org/keycodemapdb.git

libslirp

Mirror of https://gitlab.freedesktop.org/slirp/libslirp

linux

Linux kernel source tree

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

magicore

An out-of-order processor that supports multiple instruction sets.

meson

The Meson Build System

openssl

TLS/SSL and crypto library

qat_engine

qdt

QEMU Development Toolkit

qemu

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

qemu_blog

A series of posts about QEMU internals

r2vm

Rust RISC-V Virtual Machine

ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

riscv-asm-manual

RISC-V Assembly Programmer's Manual

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

riscv-isa-manual

RISC-V Instruction Set Manual

riscv_isa_spec_tour

Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)

risu

My copy of Pete Maydell's risu code generator/tester (see git://git.linaro.org/people/pmaydell/risu.git)

rvjit-aa64

RISC-V static binary translator targeting AArch64.