There's an alias for the RV32I version of SLLI: <div class="Box Box--condensed my-

RV64 uses the bit 25 as the 6-th bit for shamt. <span class="email

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Why shamt in this repo is [25:20] about riscv-opcodes HOT 6 CLOSED

riscv commented on August 26, 2024

Why shamt in this repo is [25:20]

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Comments (6)

aswaterman commented on August 26, 2024 1

There's an alias for the RV32I version of SLLI:

Line 2 in 8d59eaa

@slli.rv32 rd rs1 31..25=0 shamtw 14..12=1 6..2=0x04 1..0=3

Note that one uses shamtw, which uses bits 24:20.

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furuame commented on August 26, 2024

It means bit24-20 in Python

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Phantom1003 commented on August 26, 2024

It means bit24-20 in Python

But why rd is defined:

arglut['rd'] = (11,7)

[11:7] follows description in spec

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kito-cheng commented on August 26, 2024

RV64 uses the bit 25 as the 6-th bit for shamt.

On Wed, Aug 19, 2020 at 10:51 PM Yan ***@***.***> wrote: It means bit24-20 in Python No, I do not think so, rd is defined: arglut['rd'] = (11,7) [11:7] follows description in spec [image: image] <https://user-images.githubusercontent.com/39120057/90650422-71198800-e26e-11ea-83e2-f91f4b2f50c2.png> — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#47 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAUY24MQEUPS4E54DNSSRADSBPRHTANCNFSM4QEZSCVA> .

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kito-cheng commented on August 26, 2024