Comments (2)
IIRC, I used ignore
out of laziness, given the plethora of RVC field types. I don't see any technical disadvantage to your proposal.
If this were to be used by other tools, it might be useful to name distinct fields when the interpretations are different, even when they occupy the same bit positions. For load instructions, for example, c.lwimm
and c.ldimm
could correspond to the same instruction bits, but they expand to different RVI immediates.
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+1 to both tommythorn's comment (request) and aswaterman's proposal to distinguish fields with the same bit positions but different meanings. I wish I had the time to implement this improvement, but I don't.
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Related Issues (20)
- Arguments Position and Range
- RV32_I has only 3 instructions? HOT 3
- Conflicts with shared opcodes HOT 5
- instr_dict should contain instruction format HOT 9
- Split `rv_zicbo` file into `zicbom`, `zicboz`, `zicbop`
- Change constant.py to constant.json HOT 1
- Constants.py is duplicated between riscv-opcodes and riscv-config? HOT 4
- Cannot turn tex files into PDF HOT 2
- Use ULL (unsigned long long) suffixes in generated encoding.h file HOT 2
- encoding conflict between Zfbf/fcvt.bf16.s and Zfa/fround.h HOT 4
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- Wrong encoding of fmvp.d.x instruction HOT 4
- Use fd/fs# for floating point operands HOT 6
- redefined instruction: c.ld in rv64_c and rv128_c
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- Unclear grammar / Exceptions to instruction syntax HOT 7
- Small Typo in the readme HOT 1
- In encoding.h, MSTATEEN0_HENVCFGH is wrong HOT 2
- Make instr_dict.yaml more detailed HOT 1
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