Comments (1)
It has: https://github.com/riscv/riscv-opcodes/blob/master/LICENSE
from riscv-opcodes.
Related Issues (20)
- Arguments Position and Range
- RV32_I has only 3 instructions? HOT 3
- Conflicts with shared opcodes HOT 5
- instr_dict should contain instruction format HOT 9
- Split `rv_zicbo` file into `zicbom`, `zicboz`, `zicbop`
- Change constant.py to constant.json
- Constants.py is duplicated between riscv-opcodes and riscv-config? HOT 4
- Cannot turn tex files into PDF HOT 2
- Use ULL (unsigned long long) suffixes in generated encoding.h file HOT 2
- encoding conflict between Zfbf/fcvt.bf16.s and Zfa/fround.h HOT 4
- Wrong encoding of Vector Mask-Register Logical Instructions HOT 2
- Wrong encoding of fmvp.d.x instruction HOT 4
- Use fd/fs# for floating point operands HOT 6
- redefined instruction: c.ld in rv64_c and rv128_c
- Wrong encoding for C extension on golang
- Unclear grammar / Exceptions to instruction syntax HOT 7
- Small Typo in the readme HOT 1
- In encoding.h, MSTATEEN0_HENVCFGH is wrong HOT 2
- Make instr_dict.yaml more detailed HOT 1
- Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH HOT 1
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